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systemverilog

Here are 2,527 public repositories matching this topic...

bojieli / OpenTallas

Open research toward model-specific mask-ROM LLM inference silicon: analytical studies, an ABI 3.0 compiler/runtime and cycle model, synthesizable RTL, and open-PDK physical evidence — gated against itself by a 19-rung board that is deliberately mostly red.

reproducible-research accelerator systemverilog computer-architecture hardware-acceleration yosys verilator openroad open-source-eda llm-inference asap7 mask-rom

Updated Oct 7, 2026
Verilog

chef5531 / kian

Enable multi-agent workflows with built-in document management, task automation, and app development for efficient knowledge and project handling.

python linux education flask asic cpu fpga encoder verilog systemverilog vga system-on-chip memorize kiandamuzik comunidadeandroidangola bukaapp github-config rv32ima tinytapeout

Updated Oct 7, 2026
TypeScript

etcimon / GSys-LibreCore

A source-available, Linux-capable RISC-V application-class super-processor — and the super-intelligence agentic custom-build platform that carries it from core to silicon through bios and pytorch to any GHz desired.

rust cpu eda systemverilog out-of-order risc-v static-timing-analysis

Updated Oct 7, 2026
D

KarpelesLab / reticle

A VHDL and Verilog compiler written from scratch in Rust, with no third-party crates: simulation, synthesis, formal verification, FPGA place-and-route, bitstream generation and JTAG programming.

rust simulator asic fpga compiler vhdl eda verilog synthesis systemverilog no-dependencies hdl formal-verification jtag bitstream static-timing-analysis place-and-route

Updated Oct 7, 2026
Rust

Kylanfang / ArchiLens

面向 DeepSeek Harness 的可溯源 RTL 拓扑图插件：扫 Verilog/SystemVerilog 生成带 file:line 证据的模块拓扑 SVG，交付前复核幻觉率、非零拒交；零依赖离线，接 RTLens 证据后端。

fpga topology rtl verilog systemverilog anti-hallucination deepseek-harness dsh-plugin

Updated Oct 7, 2026
JavaScript

Kylanfang / RTLens

RTLens：给 FPGA 工程师和 AI 助手的 Verilog/SystemVerilog 代码智能引擎——LSP/MCP/CLI 提供层级树、端口一致性检查、变更影响分析与机器可读证据导出；纯 Python 零依赖，可选 Verible 后端。

python fpga mcp static-analysis rtl verilog systemverilog lsp

Updated Oct 7, 2026
Python

omrawaley / tt-pong-asic

asic fpga pong game-development verilog systemverilog fpga-game hdl pong-game vga verilog-hdl vga-driver hackclub vga-controller fpga-programming asic-design tinytapeout asics hackclub-asic

Updated Oct 7, 2026
Verilog

tenstorrent / rv_tester

Risc-v cpu testing component (Testbench) written in sv and c++

cpp verification dpi systemverilog risc-v tenstorrent

Updated Oct 7, 2026
C++

Sarkar22 / hades-v-plus

Extended RISC-V soft core targeting the Basys3 FPGA: RV32IM + Zba + Zicsr/Zifencei/Zicntr on a 5-stage in-order pipeline with a branch predictor. Runs FreeRTOS with an interactive shell in Verilator simulation; formally verified multiply/divide unit. Built on TU Graz's HaDes-V.

cpu fpga riscv freertos vivado systemverilog computer-architecture rtos hdl formal-verification risc-v basys3 wishbone soft-core verilator processor-design artix-7

Updated Oct 7, 2026
SystemVerilog

boldaxolotl / booley

The open-source agentic RTL IDE

Updated Oct 7, 2026
Python

api-evangelist / chips-alliance

CHIPS Alliance — independent third-party profile of a public API surface, by API Evangelist. CHIPS Alliance is a Linux Foundation project (founded in 2019) that develops open-source hardware (silicon) and tools, including CPUs, SoC subsystems, peripherals, IP blocks, and FPGA tooling.

open-source fpga hardware open-hardware eda chisel systemverilog soc risc-v silicon linux-foundation sifive apis-json

Updated Oct 7, 2026

yaguboo / Arcade-ShadowForce_MiSTer

Shadow Force / Henshin Ninja (Technos, 1993) arcade core for MiSTer FPGA - 3 sets. Hobby project.

fpga arcade mister systemverilog mister-fpga technos

Updated Oct 7, 2026
SystemVerilog

oddball / ipxact2systemverilog

Translates IPXACT XML to synthesizable VHDL or SystemVerilog

vhdl verilog ip-xact systemverilog

Updated Oct 7, 2026
Python

aurig-fpga / aurig-doc

VHDL documentation generator for the AURIG open-source FPGA tooling stack — Markdown/HTML docs from a single file or a whole project. Consumes aurig-core.

fpga vhdl tcl eda rtl verilog systemverilog hardware-designs hdl documentation-generator

Updated Oct 7, 2026
Tcl

aerovexhq / axiom

High-performance, in-RAM HDL processor, Cranelift JIT simulator, and physics-informed silicon telemetry engine in Rust.

react rust fpga simulation eda verilog systemverilog jit-compiler hdl vcd tauri saif static-timing-analysis cranelift power-telemetry delta-cycles

Updated Oct 7, 2026
TypeScript

dau-dev / dau-build

Build tools for dau projects

python fpga verilog xilinx vivado systemverilog hdl system-verilog verilator cocotb

Updated Oct 7, 2026
Python

dau-dev / dau-utils

Utilities for dau projects

python fpga hardware verilog systemverilog hdl

Updated Oct 7, 2026
Python

PulsePins

rokzitko / PulsePins

PulsePins provides a programmable timing core for dozens of digital pins, suitable for pulse sequences, triggers, multiplexing, and general lab ‘digital glue’

fpga timing instrumentation verilog systemverilog lab-automation experimental-physics quantum-control triggering soc-fpga pulse-sequencer

Updated Oct 7, 2026
C++

GauthamMK-0 / PolyFlow-NPU

Multi-tenant Neural Processing Unit (NPU) architecture featuring runtime-reconfigurable systolic array fission and per-region polymorphic dataflow switching for AI workloads..

rtl systemverilog computer-architecture cadence npu

Updated Oct 7, 2026
SystemVerilog

khademullah / TLP2HDL

Pcap2HDL for PCIe TLPs — replay pcieshark/QEMU traces into Verilator, teaching AXIS beats, GTKWave, DPI-C and HDL Match gate.

asic fpga qemu systemverilog pcie verilator tlp axi-stream hardware-simulation dpi-c hardware-software-co-design pcieshark

Updated Oct 7, 2026
SystemVerilog

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