A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
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Dec 2, 2019 - Verilog
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place-and-route
Here are 35 public repositories matching this topic...
SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
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Aug 21, 2024 - C++
Electronic design automation for Minecraft
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May 3, 2019 - Python
LangChain based VLSI flow that is able to generate required HDL, testbench, design creation and implementaion scripts.
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Jul 15, 2023 - Makefile
Open-Source VHDL Synthesis for Alhambra II FPGA Board
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Jan 19, 2025 - VHDL
SerDes RTL design, verification using UVM and Physical design.
fsm serdes synthesis piso-shift-register highspeed encoder-decoder sipo timing-analysis physical-design place-and-route
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May 26, 2024 - Verilog
A VHDL and Verilog compiler written from scratch in Rust, with no third-party crates: simulation, synthesis, formal verification, FPGA place-and-route, bitstream generation and JTAG programming.
rust simulator asic fpga compiler vhdl eda verilog synthesis systemverilog no-dependencies hdl formal-verification jtag bitstream static-timing-analysis place-and-route
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Oct 27, 2026 - Rust
Lark based DEF file parser
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Jun 4, 2023 - Python
Parameterized binary-tree LUT network verified with a full UVM environment, then carried through an automated RTL-to-GDSII flow to 0-DRC signoff (GPDK045, 250x250 um)
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Sep 1, 2026 - Verilog
Open-source EDA toolchain: a Rust-based HDL (Silica) compiling to Verilog-2005, plus a full digital design suite — lint, format, synth, sim, place & route, DRC — and a Tauri desktop IDE.
rust eda verilog synthesis hdl vlsi digital-design hardware-description-language place-and-route chip-design
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Sep 15, 2026 - Rust
Pipelined odd-even transposition sorter taken through a full RTL-to-GDSII flow (Genus + Innovus, GPDK045): 0 DRC, GDSII sign-off, gate-level SDF verification pre- and post-route
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Sep 3, 2026 - Verilog
32-bit ALU, 14 ops — full RTL-to-GDS: Cadence Genus synthesis, Innovus P&R, DRC clean on 45nm CMOS
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Jun 27, 2026 - Verilog
From an AI workload or your own RTL to a chip GDS on IHP SG13G2, checked with DRC and LVS: architecture exploration with every decision explained, X-HEEP SoC or AXI4 IP generation, and an open digital flow from lint and formal to DFT, pad ring and signoff. MCP server.
asic mcp eda design-space-exploration systemverilog formal-verification yosys risc-v open-source-hardware verilator cocotb axi4 openroad place-and-route hardware-accelerator llm-inference x-heep model-context-protocol librelane ihp-sg13g2
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Oct 25, 2026 - Python
Full RTL-to-GDSII ASIC implementation of a 100MHz low-power multi-clock digital communication SoC in TSMC 130nm, featuring robust CDC, Integrated Clock Gating (ICG), and complete physical sign-off.
dft verilog uart fifo soc vlsi digital-design low-power clock-domain-crossing static-timing-analysis gate-level-simulation asic-design place-and-route rtl-to-gdsii tsmc-130nm
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Oct 10, 2026 - Verilog
Circuit and system design portfolio - DMT wireline transceiver DSP (14nm FinFET tape-out), on-chip adaptive bit/power loading, multi-lane chip-to-chip interface, RFSoC real-time verification, 28nm back-end flow, and analog/full-custom design
portfolio fpga signal-processing dsp matlab vhdl verilog vlsi semiconductor mixed-signal analog-design asic-design place-and-route rtl-design rfsoc wireline-communication
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Sep 17, 2026
Detailed placement over the OpenDB design database: placement legality checking.
rust asic eda opendb physical-design openroad place-and-route legalization open-source-silicon detailed-placement
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Oct 25, 2026 - Rust
Run physical-design stages and inspect timing for a netlist through an MCP server
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Oct 5, 2026 - TypeScript
32-bit RISC-V ASIC physical design featuring a custom standard cell library, bit-sliced datapath routed in Cadence Virtuoso, and automated Cadence Innovus implementation.
asic computer-architecture vlsi risc-v cadence-virtuoso drc tcl-scripts physical-design place-and-route freepdk45 cadence-innovus standard-cells cmos-logic lvs-calibre
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Aug 13, 2026 - Tcl
Formalizing place-and-route timing-closure bounds.
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May 8, 2026 - Rocq Prover
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