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ultraembedded / core_jpeg

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High throughput JPEG decoder in Verilog for FPGA

fpga mjpeg verilog motion-jpeg verilog-hdl jpeg-decoder axi-stream

Updated Mar 5, 2022
Verilog

KastnerRG / cgra4ml

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An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

asic ai fpga neural-network cnn dnn verilog systemverilog axi-stream asic-design hls4ml

Updated Sep 6, 2026
SystemVerilog

This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core

fpga udp verilog axi-stream

Updated Mar 15, 2022
Verilog

fcayci / vhdl-axis-uart

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UART to AXI Stream interface written in VHDL

fpga vhdl uart axi-stream

Updated Oct 20, 2022
VHDL

DOUDIU / AXIS-AXI4-AXIS

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This project is designed to delay the output of the video stream in AXI-STREAM format.

fpga ddr axi-stream axi-full

Updated Jul 14, 2024
Verilog

shashankov / ReCONNECT

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ReCONNECT: FPGA Optimized RTL-Native Parameterized Network-on-Chip

generator fpga system-verilog noc network-on-chip axi-stream

Updated Aug 12, 2026
SystemVerilog

catarinaacsilva / vivado-xilinx-tutorials

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Tutorials or projects example to use Vivado 2019.2 and Vitis

fpga hardware timer software rtos axi-dma memory-mapped axi-stream

Updated Oct 27, 2020
VHDL

Yong12315 / FPGA-Engineering-Notes

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Engineering notes and reproducible FPGA examples from real-world development, including RTL design, simulation, verification and debugging.

fpga zynq matlab rtl verilog chinese xilinx vivado digital-signal-processing rapidio engineering-notes axi-stream timing-analysis fpga-tutorial

Updated Oct 13, 2026
Verilog

Lamagraph / pci-ddr-gowin-tangmega138kpro

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Gowin tangmega138k Pro pci+ddr demo

fpga driver pcie axi-stream ddr3 axi4 gowin gowin-fpga ddr-demo tangmega138k-pro pci-demo

Updated Oct 22, 2026
Verilog

ShoukathAli23 / Image-Video-Processing-on-FPGA

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Various video processing projects will be shared here

fpga vhdl image-processing video-processing pynq-z1 axi-stream

Updated May 26, 2020
Jupyter Notebook

IEEEYorkU / lascon-ip

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LASCON — A synthesizable SystemVerilog implementation of the NIST SP 800-232 Ascon lightweight cryptographic standard. Supports AEAD128, Hash256, XOF128, and CXOF128.

nist cryptography fpga systemverilog axi-stream lightweight-cryptography hardware-accelerator

Updated Oct 10, 2026
SystemVerilog

gururavi / rtl

Star

Synchronous and Asynchronous FIFO with AXI interface

fpga pipeline rtl synthesis systemverilog fifo axi floating-point-arithmetic axi-stream axi4

Updated Nov 20, 2019
SystemVerilog

MasterPlayer / axis_uart_bridge

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FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol

fpga zynq xilinx uart systemverilog artix uart-tx axi-stream uart-rx

Updated Dec 2, 2021
SystemVerilog

pkill37 / fpga-gradient-descent

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FPGA benchmark of vectorized gradient descent on linear regression

fpga linear-regression vhdl xilinx gradient-descent microblaze axi axi-stream

Updated Oct 14, 2026
VHDL

LLYniku / Ernic_cmac

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Alveo U50 FPGA RDMA transmit integration of AMD/Xilinx ERNIC and CMAC UltraScale+ over 512-bit AXI-Stream

fpga verilog xilinx rdma roce vivado cmac axi-stream alveo-u50

Updated Jul 24, 2026
Verilog

amamory / axis-skidbuffer

Star

A one-position buffer compatible with AXI Stream interface

vivado axi-stream skidbuffer

Updated May 23, 2023
Tcl

Yuval-Peleg / udp-offload-engine-vhdl

Star

UDP/IPv4/Ethernet offload engine in VHDL for the Xilinx XXV Ethernet MAC IP.

fpga udp vhdl ipv4 arp xilinx vivado ethernet network-stack axi-stream 10gbe

Updated Oct 18, 2026
VHDL

aryan-programmer / axi_gen_and_sum_primes_fpga

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A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

Updated Nov 21, 2023
TeX

amamory / axis-skidbuffer-lfsr

Star

An IP used for testing AXI stream protocols. It uses a LFSR to generate ready and valid signals

vivado lfsr axi-stream skidbuffer

Updated Aug 10, 2020
Tcl

ridash2005 / Bit-Serial_Neural_Computation_Engine

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High-efficiency, resource-optimized Neural Network Computation Engine in SystemVerilog. Leverages bit-serial arithmetic to minimize hardware footprint (LUTs/Registers) without compromising precision. 🏆 Gold Winner @ VLSI Hackathon, NIT Jamshedpur.

fpga systemverilog computer-architecture vlsi hardware-acceleration axi-stream edge-ai rtl-design neural-network-accelerator deep-learning-hardware hackathon-winner-project asic-design-fpga-ai-ml-low-power

Updated May 14, 2026
SystemVerilog

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axi-stream

Here are 85 public repositories matching this topic...

ultraembedded / core_jpeg

KastnerRG / cgra4ml

alknvl / axis_udp

fcayci / vhdl-axis-uart

DOUDIU / AXIS-AXI4-AXIS

shashankov / ReCONNECT

catarinaacsilva / vivado-xilinx-tutorials

Yong12315 / FPGA-Engineering-Notes

Lamagraph / pci-ddr-gowin-tangmega138kpro

ShoukathAli23 / Image-Video-Processing-on-FPGA

IEEEYorkU / lascon-ip

gururavi / rtl

MasterPlayer / axis_uart_bridge

pkill37 / fpga-gradient-descent

LLYniku / Ernic_cmac

amamory / axis-skidbuffer

Yuval-Peleg / udp-offload-engine-vhdl

aryan-programmer / axi_gen_and_sum_primes_fpga

amamory / axis-skidbuffer-lfsr

ridash2005 / Bit-Serial_Neural_Computation_Engine

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