Programmable 3x3 convolution engine + fixed Sobel core for Zynq-7020: RTL, testbenches, golden model, Vivado reports
FPGA PL 부분, I2C FSM로직 구현 및 AXI-Lite와 AXI-Stream을 이용해서 DMA구현, AI연산을 DPU로 구현해 AI를 하드웨어로 가속
Zynq-7000 SoC AXI DMA memory-streaming pipeline with custom AXI4-Stream Verilog RTL datapath, closed timing at 100 MHz, Vivado automation, and Jupyter benchmarking.
This repository will host slides and support code for the webinar "Latency Insensitive Design: Theoretical and Practical Considerations".
Zynq UltraScale+ MPSoC 환경에서 고속으로 입력되는 이미지 데이터를 실시간으로 처리하기 위한 FPGA 기반 IP 코어를 설계하고 검증한 프로젝트이다.
SystemVerilog AXI4-Stream beat FIFO preserving TKEEP/TLAST, with scoreboard simulation, formal safety checks, bug-injection testing, and GitHub Actions CI.
Deterministic 0/1-Cycle Cut-Through NASDAQ ITCH 5.0 Parser in SystemVerilog. SOTA HFT FPGA/ASIC IP Core with Formal Verification.
ZCU104 AES-128-GCM authenticated image encryption using custom Verilog, AXI4-Stream, AXI DMA, Cortex-A53 and Python reference verification.
A high-performance AES-128 Hardware Accelerator implemented in SystemVerilog. Optimized for Xilinx Artix-7 FPGAs, featuring a dual AXI4-Lite/Stream interface and a BRAM-less S-Box architecture using Composite Field arithmetic. Achieves 150MHz timing closure with area-optimized iterative processing.
Real-time 2D FFT edge detection accelerator on Zynq-7000, featuring a memory-efficient Radix-2 SDF architecture and zero-latency Ping-Pong buffering.
Parametrizable UART controller in Verilog with AXI-Stream interface, configurable baud rate, oversampling ratio, parity mode, stop bits, and regression testbench for verification.
Real-time VGA video chain on the ZedBoard (Zynq-7000): test pattern, AXI4-Stream, Vitis HLS inverter and overlay IPs, 640x480 output
An AXI4/5-Stream PID controller
Original UVM verification environment for a fictional AXI4-Stream-to-internal-bus bridge IP (StreamBridge) -- tag-indexed scoreboarding, split completer/DMA environments, wide-bus lane checking.
An AXI4/5-Stream exponential moving average (EMA) filter
Parametric FIR filter IP core in SystemVerilog. Transposed direct-form, AXI4-Stream, bit-exact vs scipy.signal.lfilter. For DSP/SDR/audio/ML.
8 SystemVerilog FIFO designs formally verified (SymbiYosys BMC + k-induction), mutation-tested, FPGA-characterized — green CI
A test IP that receives a packet from the NoC, increments its the payload, and sends the packet back to the source
FPGA PL 부분, I2C FSM로직 구현 및 AXI-Lite와 AXI-Stream을 이용해서 DMA구현, AI연산을 DPU로 구현해 AI를 하드웨어로 가속
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