AXI4 and AXI4-Lite interface definitions
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Sep 20, 2020 - SystemVerilog
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axi4-stream
Here are 30 public repositories matching this topic...
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
simulation vhdl verification vip tlm testbench osvvm simulation-modeling axi4 axi4-lite axi4-stream verification-component
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Oct 21, 2026 - VHDL
SystemVerilog AXI verification library and video-DMA IP: AXI4/Lite/Stream BFMs, triple-buffer VDMA, and multi-tap temporal VDMA with byte-exact real-image round-trip tests. Verilator · Yosys · Docker · CI.
docker verification image-processing video-processing systemverilog fifo cdc yosys dma bfm verilator sva cdma axi4 axi4-lite axi4-stream github-actions vdma skidbuffer data-movement
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Jul 5, 2026 - SystemVerilog
FPGA PL 부분, I2C FSM로직 구현 및 AXI-Lite와 AXI-Stream을 이용해서 DMA구현, AI연산을 DPU로 구현해 AI를 하드웨어로 가속
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Dec 15, 2025 - Verilog
An AXI4/5-Stream PID controller
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Sep 13, 2025 - VHDL
Verilog image signal processor with AXI4-Stream interfaces — RTL ISP pipeline for FPGA SoC integration.
open-source computer-vision fpga embedded-systems rtl verilog hdl soc axi4 axi4-stream hardware-design image-signal-processing
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Jun 10, 2026 - Python
Programmable 3x3 convolution engine + fixed Sobel core for Zynq-7020: RTL, testbenches, golden model, Vivado reports
computer-vision fpga zynq image-processing rtl verilog vivado sobel axi4-stream hardware-accelerator
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Oct 5, 2026 - Verilog
A collection of formal properties for hardware buses, and cores using them.
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Feb 22, 2021 - Verilog
Parametrizable UART controller in Verilog with AXI-Stream interface, configurable baud rate, oversampling ratio, parity mode, stop bits, and regression testbench for verification.
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Jun 16, 2026 - Verilog
Zynq-7000 SoC AXI DMA memory-streaming pipeline with custom AXI4-Stream Verilog RTL datapath, closed timing at 100 MHz, Vivado automation, and Jupyter benchmarking.
fpga verilog vivado pynq soc axi-dma digital-design zynq-7000 axi4-stream static-timing-analysis hardware-software-codesign
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Sep 1, 2026 - Tcl
This repository will host slides and support code for the webinar "Latency Insensitive Design: Theoretical and Practical Considerations".
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Apr 24, 2025 - SystemVerilog
Real-time VGA video chain on the ZedBoard (Zynq-7000): test pattern, AXI4-Stream, Vitis HLS inverter and overlay IPs, 640x480 output
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Oct 28, 2026 - VHDL
Zynq UltraScale+ MPSoC 환경에서 고속으로 입력되는 이미지 데이터를 실시간으로 처리하기 위한 FPGA 기반 IP 코어를 설계하고 검증한 프로젝트이다.
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Dec 21, 2025 - Verilog
Original UVM verification environment for a fictional AXI4-Stream-to-internal-bus bridge IP (StreamBridge) -- tag-indexed scoreboarding, split completer/DMA environments, wide-bus lane checking.
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Aug 18, 2026 - SystemVerilog
SystemVerilog AXI4-Stream beat FIFO preserving TKEEP/TLAST, with scoreboard simulation, formal safety checks, bug-injection testing, and GitHub Actions CI.
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Oct 25, 2026 - SystemVerilog
Deterministic 0/1-Cycle Cut-Through NASDAQ ITCH 5.0 Parser in SystemVerilog. SOTA HFT FPGA/ASIC IP Core with Formal Verification.
asic fpga fintech verilog low-latency hft systemverilog formal-verification cocotb axi4-stream nasdaq-itch cut-through
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Aug 27, 2026 - SystemVerilog
ZCU104 AES-128-GCM authenticated image encryption using custom Verilog, AXI4-Stream, AXI DMA, Cortex-A53 and Python reference verification.
fpga verilog aes-gcm vivado aes128 image-encryption axi-dma hardware-security hardware-verification axi4-stream rtl-design vitis image-encryption-algorithm zcu104 zynq-ultrascale image-encryption-decryption
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Oct 25, 2026 - C
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