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@standardgalactic
Cogito Ergo Sum standardgalactic
𝘏𝘰𝘮𝘦 𝘰𝘧 𝘵𝘩𝘦 𝚂𝚝𝚊𝚗𝚍𝚊𝚛𝚍 𝙶𝚊𝚕𝚊𝚌𝚝𝚒𝚌 𝙰𝚕𝚙𝚑𝚊𝚋𝚎𝚝

Xanadu Canada

@aritramanna
Aritra Manna aritramanna
I’m a Senior Pre-Silicon Design Verification Engineer (5+ years) working at the intersection of CPU, GPU/SIMT, and accelerator microarchitecture.

Bangalore, India

@Alaa-Elshahawy
Alaa Elshahawy Alaa-Elshahawy
Digital IC Design & Verification Engineer

Cairo

@jamestiotio
James R T jamestiotio
"Any sufficiently advanced technology is indistinguishable from magic." - Sir Arthur Charles Clarke

@facebook The edge of knowing

@muscoder
Mustafa Tosun muscoder

Ozyegin University Istanbul/TURKEY

@rassB
rassB
FOS(S/H) Enthusiast.

CentraleSupélec Rennes, France.

@unforgiven512
Gerad Munsch unforgiven512
I'm a proud father, enjoy amateur radio operations as @KD9QZO on the air, and under @unforgiven-development I enjoy working on a variety of embedded systems.

@unforgiven-development Hainesville, IL, USA

@paulinog
Guilherme Paulino paulinog
X-ray detectors R&D. Edge Computing.

@slaclab Menlo Park CA, USA

@gmorales08
Gabriel Morales gmorales08
Embedded software developer. Low level enjoyer.

Madrid, Spain

@prajwaltr
Prajwal T R prajwaltr
Pre final year B.E student, Interested in VLSI and Programming.

Karnataka, India.

@paranlee
Paran Lee paranlee
Linux Kernel (≥ v6.x.y) | ARM64 | RISC-V | BEAM | Container Lover

Ericsson LG 51, Gasan digital 1-ro, Geumcheon-gu, Seoul, Republic of Korea

@Cuizhenzhen
崔震 Cuizhenzhen
Soc designand verification

3peak Tianjin

@yasssuz
Karim yasssuz
Web3 Software Engineer | Go | Rust | Typescript | Blockchain Researcher | Performance & Scalability Enthusiast | Privacy Freak | Polyglot

Binance | Trust Wallet

@pConst
Konstantin Pavlov pConst
Digital electronics, FPGAs, multi-gigabit interfaces

Saint-Petersburg, Russia

@euripedesrocha
Euripedes euripedesrocha

@espressif Czech Republic

@iDoka
Dmitry Murzinov iDoka
Hardware Imagineer | Digital IC Design Engineer | Automotive Electronics Enthusiast

@dokard @deepware-ai Error: Unable to resolve

@yrrapt
Thomas Parry yrrapt
Analogue/Digital ASIC design, RF/SDR, High Reliability and Space

The Netherlands

@igor-dimi
Igor Dimitrov igor-dimi
systematic programmer ~ student
@umarcor
Unai Martinez-Corral umarcor

UPV/EHU Bilbo, Bizkaia, Euskadi, Spain, Europe

@bpmasc
bpmasc

Oxford, U.K.

@tmeissner
T. Meissner tmeissner
FPGA-Engineer doing design and verification using VHDL, SystemVerilog, SVA and PSL.

Dresden, Germany

@kelu124
K. Ghosh kelu124
Purpose-driven digit, also doing hardware, ultrasound imaging, n00b in Python, and experimenting in LLMs and others =

Paris

@dpretet
Damien Pretet dpretet
FPGA/ASIC Design Engineer

France

@lifa123
muuk lifa123
security

china

@mariuselv
mariuselv mariuselv
VHDL, Python, UVVM

Bitvis / Inventas Norway