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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects.

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  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4.8k 660

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.9k 1.3k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 2k 309

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1.4k 400

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 971 246

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 746 180

Repositories

Showing 10 of 122 repositories
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    chipsalliance/caliptra-mcu-sw's past year of commit activity
    Rust 41 Apache-2.0 90 164 (5 issues need help) 100 Updated Oct 2, 2026
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl's past year of commit activity
    SystemVerilog 155 Apache-2.0 108 119 (2 issues need help) 41 Updated Oct 2, 2026
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    chipsalliance/caliptra-ss's past year of commit activity
    SystemVerilog 54 Apache-2.0 63 92 34 Updated Oct 2, 2026
  • Cores-VeeR-EL2 Public

    VeeR EL2 Core

    chipsalliance/Cores-VeeR-EL2's past year of commit activity
    SystemVerilog 345 Apache-2.0 113 44 12 Updated Oct 2, 2026
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel's past year of commit activity
    Scala 4,801 Apache-2.0 660 352 (1 issue needs help) 156 Updated Oct 2, 2026
  • firrtl-spec Public

    The specification for the FIRRTL language

    chipsalliance/firrtl-spec's past year of commit activity
    TeX 67 33 27 20 Updated Oct 2, 2026
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw's past year of commit activity
    Rust 171 Apache-2.0 130 238 (8 issues need help) 83 Updated Oct 1, 2026
  • Caliptra Public

    Caliptra IP and firmware for integrated Root of Trust block

    chipsalliance/Caliptra's past year of commit activity
    478 Apache-2.0 78 123 11 Updated Oct 2, 2026
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests's past year of commit activity
    SystemVerilog 397 ISC 104 48 (4 issues need help) 38 Updated Oct 2, 2026
  • usb2 Public

    USB core

    chipsalliance/usb2's past year of commit activity
    VHDL 1 Apache-2.0 6 23 1 Updated Oct 1, 2026
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