Issues

• [RTL][IFU/DCLS] Core-side iCache ECC/Parity check enable (ic_rd_bank_check_en) and rotator offset (ic_rd_addr_lo) are driven from EL2_IC_DATA outside DCLS

  Bug

  chipsalliance/Cores-VeeR-EL2#569 · Filter by author samipmodi323 opened on Oct 5, 2026
  

• [COVERAGE]: DCLS Functional Coverage Implementation plan

  Task

  chipsalliance/Cores-VeeR-EL2#567 · Filter by author samipmodi323 opened on Oct 2, 2026
  

• [BUG] DCCM write readback error feature breaks single bit ecc correction

  chipsalliance/Cores-VeeR-EL2#566 · Filter by author Nitsirks opened on Oct 1, 2026

• Writes to read-only CSRs (cycle, instret, hpmcounterN, CSR address bits [11:10] = 11) do not raise an illegal-instruction exception

  chipsalliance/Cores-VeeR-EL2#563 · Filter by author CacheGuruinthemaking opened on Oct 1, 2026

• [BUG] ICCM XOR Infection feature causes double bit ECC error in CAM logic

  chipsalliance/Cores-VeeR-EL2#562 · Filter by author Nitsirks opened on Sep 30, 2026
  2

  

• [BUG] PMP without Smepmp: U-mode accesses succeed when every PMP entry is OFF

  chipsalliance/Cores-VeeR-EL2#558 · Filter by author CacheGuruinthemaking opened on Sep 28, 2026

• [BUG] Writes to pmpcfg/pmpaddr/mseccfg are not synchronized: the next two loads/stores are PMP-checked against the old settings

  chipsalliance/Cores-VeeR-EL2#557 · Filter by author CacheGuruinthemaking opened on Sep 26, 2026
  2

• MCGC register defaults

  chipsalliance/Cores-VeeR-EL2#542 · Filter by author elecharo opened on Sep 11, 2026

• [BUG/DOC] rvecc_decode blind spot: Single-bit error on MSB parity bit goes completely undetected when sed_ded = 1

  chipsalliance/Cores-VeeR-EL2#521 · Filter by author ShashankVM opened on Aug 2, 2026
  1

• [VAL] Test DCCM write readback check

  chipsalliance/Cores-VeeR-EL2#512 · Filter by author h-filali opened on Jul 23, 2026
  

• [VAL] Test: Add separate tests for signals skipped in dcls.c which breaks code execution.

  chipsalliance/Cores-VeeR-EL2#494 · Filter by author samipmodi323 opened on Jul 7, 2026
  

• Triple modular redundancy (TMR) support

  chipsalliance/Cores-VeeR-EL2#493 · Filter by author mkurc-ant opened on Jul 7, 2026

• [VAL] Test ICache Address Infection Feature

  chipsalliance/Cores-VeeR-EL2#491 · Filter by author nasahlpa opened on Jul 3, 2026
  2

  

• [VAL] Check register file DCLS comparison

  chipsalliance/Cores-VeeR-EL2#483 · Filter by author nasahlpa opened on Jun 30, 2026
  4

  

• [devel] Enable nix and/or Python virtual environment setup similar to i3c-core repository

  enhancement
  Feature

  chipsalliance/Cores-VeeR-EL2#455 · Filter by author moidx opened on May 27, 2026
  2

• Updates for missing files/instances in prefix script

  chipsalliance/Cores-VeeR-EL2#440 · Filter by author calebofearth opened on Jan 15, 2026

• Files in design/dmi/ have .v extensions, but use SV constructs

  chipsalliance/Cores-VeeR-EL2#439 · Filter by author martinpriestley opened on Dec 23, 2025

• common_defines.vh isn't a header

  chipsalliance/Cores-VeeR-EL2#438 · Filter by author martinpriestley opened on Dec 23, 2025

• [LINT] request to clean up a few new lint rules

  chipsalliance/Cores-VeeR-EL2#437 · Filter by author Nitsirks opened on Dec 18, 2025

• Option to disable ECC on CCMs

  enhancement
  chipsalliance/Cores-VeeR-EL2#435 · Filter by author martinpriestley opened on Dec 9, 2025
  1

• Assertion cleanup - not using clock edges or resets to check and disable assertion

  future
  chipsalliance/Cores-VeeR-EL2#433 · Filter by author clayton8 opened on Nov 7, 2025
  1

• Sync Reset Support

  enhancement
  chipsalliance/Cores-VeeR-EL2#429 · Filter by author clayton8 opened on Oct 27, 2025

• el2_param.vh is generated with named fields commented-out by default, and raw numeric values used

  enhancement
  chipsalliance/Cores-VeeR-EL2#428 · Filter by author calebofearth opened on Oct 9, 2025
  

• [Debug] Program Buffer and Quick Access

  enhancement
  chipsalliance/Cores-VeeR-EL2#426 · Filter by author clayton8 opened on Oct 1, 2025
  1

• [Debug] SOC Memory Access via Access Memory Command

  enhancement
  chipsalliance/Cores-VeeR-EL2#425 · Filter by author clayton8 opened on Oct 1, 2025