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Showing results

Open, machine-readable exchange format for chip-on-board wire bonding: die pads, PCB pads, wires. Generates KiCad symbols and footprints.

Python 2 Updated Sep 19, 2026

wafer.space bonding diagrams

Python 2 Updated Sep 21, 2026

Greyhound on IHP SG13G2 0.13 μm BiCMOS process - second tapeout

Verilog 1 1 Updated Jan 25, 2026

PDP-11/70 CPU core and SoC

VHDL 148 24 Updated Jun 10, 2024

📸 ADCs for faster image sensors

Python 13 1 Updated Oct 2, 2026

Greyhound on IHP SG13G2 0.13 μm BiCMOS process

SystemVerilog 110 9 Updated Aug 31, 2026

Games console SoC for GF180MCU process

Verilog 18 Updated Jul 14, 2026

IHP SG13CMOS5L PDK

Python 19 15 Updated Sep 23, 2026

LibreLane full-chip flow template for IHP SG13CMOS5L OpenPDK

SystemVerilog 9 2 Updated Mar 12, 2026

TinyTapeout demo pcb's RP2040 functionality

Python 27 18 Updated Sep 8, 2026

wafer.space GF180MCU Run 2

Shell 8 1 Updated Oct 5, 2026

A module for the Alibaba Cloud KU3P fpga PCIe card to access the internal general purpose I/O via SFP

Tcl 4 1 Updated Sep 13, 2026

Katze Ethernet Pmod Compatible Module

12 1 Updated Jul 26, 2026

Vivaldi Motherboard

C 1 Updated Mar 19, 2024

Wire bonded chip on board PCB designs.

12 3 Updated Oct 5, 2026

Multi-project die

Verilog 6 1 Updated Aug 15, 2026

Precheck for wafer.space MPW runs using the gf180mcu PDK

Python 9 2 Updated Aug 20, 2026

Anton's journal of interesting project stuff

G-code 11 Updated Jan 2, 2026

CMOS/ASIC reverse engineering project

5 Updated Jul 27, 2026

3.3V SRAM macros for GF180MCU, based on the original 5V SRAM macros.

Verilog 24 5 Updated Jun 19, 2026

Mirror of the Restoration of 1st Edition UNIX kernel sources from pdf document.

C 923 228 Updated Jul 20, 2021

From FPGA Gates to Scientific Calculator

C++ 133 10 Updated May 8, 2026
Python 33 10 Updated Jul 8, 2026

What if we synthesize IEEE.float_pkg?

VHDL 11 Updated Aug 6, 2026

Mirror of tachyon-da cvc Verilog simulator

C 58 28 Updated Mar 16, 2026

personal blog

JavaScript 6 Updated Oct 2, 2026

LibreLane full-chip flow template for IHP SG13G2 OpenPDK

Tcl 25 7 Updated Sep 21, 2026
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