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Home News Business

Codasip and UltraSoc combine on RISC-V

David Manners by David Manners
23rd November 2016
in Business
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Rupert Baines, CEO UltraSOC - Codasip and UltraSoc combine on RISC-V
Rupert Baines, CEO UltraSOC

Codasip, the RISC-V processor IP provider, and UltraSoC, the provider of semiconductor IP for on-chip analytics, are to integrate the Codix-Bk series of RISC-V cores with the UltraSoC environment.

As RISC-V based SoCs enter the mainstream, the need for commercial support with production-quality debug, analysis and bring-up tools become critical.

This collaboration provides the RISC-V community with capabilities that go beyond those available to proprietary processors and instruction set architectures (ISAs).

While selecting a processor and ISA is one of the first challenges for engineers in architecting a new SoC, the real difficulties come when they try to bring the design to life, to productize and optimize it in the real world. While RISC-V provides an ISA for processor IP, it does not in itself solve all the other problems of support, commercialization or development. This partnership focuses on that need. Rather than simply adapt legacy solutions to the RISC-V environment, this collaboration delivers a complete solution that will not only accelerate time-to-market, but extend analysis and improvement capabilities beyond initial deployment.

While RISC-V is establishing itself, engineers need proven development infrastructure and commercial support.

This collaboration addresses both needs: Codasip provide processor IP and infrastructure, while UltraSoC adds a toolkit for debug, optimization and analytics.

This collaboration is an example of how the open-source RISC-V ecosystem can innovate quickly to deliver more than is available with legacy proprietary architectures.

“RISC-V is rapidly becoming an exciting ISA choice for new designs, but suffers from the lack of a proven implementation platform,” says UltraSOC CEO Rupert Baines, “combining UltraSoC IP with proven Codix-Bk IP and debug environment results in a powerful SoC debug, analysis and chip-bring up environment that will dramatically accelerate development time while reducing risk for new SoC starts.”

The combined solution is available immediately. Both companies are committed to continually evolve their solutions to conform to the RISC-V foundations specifications (riscv.org).

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David Manners has more than forty-years experience writing about the electronics industry, its major trends and leading players. As well as writing business, components and research news, he is the author of the site's most popular blog, Mannerisms. This features series of posts such as Fables, Markets, Shenanigans, and Memory Lanes, across a wide range of topics.

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