RISC-V-architecture-design

#designing RISC-V architecture using Verilog HDL in XILINX VIVADO PC SUITE #each folder contains corresponding source files, input and output files, and screenshots of simulations

Name		Name	Last commit message	Last commit date
i, r, ld, s, b type instructions(no counters)		i, r, ld, s, b type instructions(no counters)
i, r, ld, s, b, uj type instructions(using counters)		i, r, ld, s, b, uj type instructions(using counters)
i_type and r_type together		i_type and r_type together
i_type instructions		i_type instructions
i_type, r_type(including ^, \|, &, <<, >>, >>>), load and store instructions(no counters)		i_type, r_type(including ^, \|, &, <<, >>, >>>), load and store instructions(no counters)
i_type, r_type(including ^, \|, &, <<, >>, >>>), load and store instructions(using counters)		i_type, r_type(including ^, \|, &, <<, >>, >>>), load and store instructions(using counters)
r_type instructions		r_type instructions
.DS_Store		.DS_Store
LICENSE		LICENSE
README.md		README.md

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