arm: dts: socfpga: Add Terasic DE-25 Standard Board Support - #1024
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alifzakuan wants to merge 2 commits into
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alifzakuan wants to merge 2 commits into
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Add dedicated device tree support for the Terasic DE-25 Standard board, which is based on Agilex5. Following Terasic's Linux device tree for DE-25 Standard configuration in which UART and board wiring differs from Altera SoCDK boards - enable UART1 instead of UART0, route console through serial0 alias, and expose a single HPS LED on GPIO port B pin 17 (active-low). Enable only the on-board peripherals present on this kit: a single RGMII Ethernet interface on gmac0 with PHY MDIO address 1, gpio1, i2c1, spi0, and usb0. The second GMAC, extra I2C/I3C buses, spi1, usb31, and NAND are left disabled. MMC retains UHS-I SDR104 mode consistent with the Altera SoCDK reference. QSPI NOR flash uses the SoCDK-style partition layout on the 256 MB device (dedicated u-boot and root regions); the QSPI controller is disabled in the U-Boot SPL device tree so that SD/MMC is the primary boot source. DRAM size is fixed at 1 GiB in the U-Boot additions. New files added: - socfpga_agilex5_de25s.dts: Main device tree - socfpga_agilex5_de25s-u-boot.dtsi: U-Boot specific additions - configs/socfpga_agilex5_de25s_defconfig: Board configuration Build system integration: - Add build target in Makefile for DE25 Standard device tree binary file Signed-off-by: Will <btdai@terasic.com.cn> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
0ccf019 ("test: py: load: check null_dev_desc_ok dispatch") added test_semihosting_load*, which bypass the existing "not hostfs" filter from d75998b ("Docker, CI: Add vexpress_fvp / vexpress_fvp_bloblist support"). That commit notes hostfs/semihosting tests trigger an FVP bug and must stay deselected until fixed. Extend TEST_PY_TEST_SPEC so the new tests are also deselected on vexpress_fvp and vexpress_fvp_bloblist. This is a temporary workaround for CI pipeline test for Terasic Agilex5 DE25 Standard board support patch upstream quality checking. Not intended to be upstreamed. Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
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Add dedicated device tree support for the Terasic DE-25 Standard board,
which is based on Agilex5.
Following Terasic's Linux device tree for DE-25 Standard configuration in
which UART and board wiring differs from Altera SoCDK boards - enable UART1
instead of UART0, route console through serial0 alias, and expose a single
HPS LED on GPIO port B pin 17 (active-low). Enable only the on-board
peripherals present on this kit: a single RGMII Ethernet interface on gmac0
with PHY MDIO address 1, gpio1, i2c1, spi0, and usb0. The second GMAC,
extra I2C/I3C buses, spi1, usb31, and NAND are left disabled.
MMC retains UHS-I SDR104 mode consistent with the Altera SoCDK reference.
QSPI NOR flash uses the SoCDK-style partition layout on the 256 MB device
(dedicated u-boot and root regions); the QSPI controller is disabled in the
U-Boot SPL device tree so that SD/MMC is the primary boot source. DRAM size
is fixed at 1 GiB in the U-Boot additions.
New files added:
Build system integration:
Please do not submit a Pull Request via github. Our project makes use of
mailing lists for patch submission and review. For more details please
see https://u-boot.readthedocs.io/en/latest/develop/sending_patches.html
The only exception to this is in order to trigger a CI loop on Azure prior
to posting of patches.