sva

12-bit SPI Master-Slave RTL design with class-based SystemVerilog verification, SVA, and functional validation.

Design Verification Engineer portfolio: SystemVerilog, UVM, SVA, APB4, AXI4-Lite, coverage, RISC-V and FPGA.

LLM-written SystemVerilog Assertions scored by an open-source model checker (EBMC) on NVIDIA's FVEval, calibrated against Jasper

Synthesizable Dual-Core 2-Way Set-Associative L1 Cache Subsystem in SystemVerilog featuring MESI snooping coherence protocol, non-blocking dual-port tags, round-robin bus arbitration, true LRU replacement, SVA assertions, and 100% functional coverage in Vivado XSIM.

SystemVerilog AXI4-Lite protocol verification environment featuring a 5-channel monitor, associative-array scoreboard, 13 SVA assertions, functional coverage closure, back-pressure testing, and negative protocol testbench.

SystemVerilog AXI4-Lite register-bank RTL with self-checking verification, assertions, randomized traffic, scoreboarding, and protocol corner-case testing.

Formal verification of a FIFO, round-robin arbiter and skid buffer with SystemVerilog Assertions, using open-source tools (EBMC, Spot)

Synthesizable AXI4 Full Slave Memory Controller and a production-grade UVM 1.2 testbench environment in SystemVerilog. Features 5-channel full-duplex transactions, FIXED/INCR/WRAP bursts, WSTRB byte masking, SVA protocol assertions, reference scoreboard, and 89.24% functional coverage.

Formal proof of an arbiter, a FIFO and an AXI4-Lite slave with SymbiYosys: 25 assertions proved unbounded, 13/13 covers reached, and a broken arbiter that passes every safety property.

Coverage-driven SystemVerilog verification of a synchronous FIFO: class-based env, SVA, 100% functional coverage across 50 seeds, plus a bug branch the TB actually catches

Constrained-random SystemVerilog verification of an AMBA APB4 register bank: scoreboard, functional coverage, SVA, VCS/Verilator

AMBA APB3 programmable timer in SystemVerilog: CONTROL/LIMIT/COUNT/STATUS, one-shot/periodic, IRQ, wait states; APB BFM + reference model + SVA

Public portfolio of APB4 and AXI4 verification methodology using SystemVerilog, UVM, SVA and coverage.

This project provides a comprehensive guide for integrating OAuth 2.0 with the SVA Identity Protocol

Django REST API backend with Google OAuth, GitHub OAuth, and custom email authentication with email verification.

LLM-generated formal assertions for RTL, proved by SymbiYosys. A measured grammar of the open-source SVA subset + counterexample-driven refinement.

SystemVerilog, UVM, and SVA verification projects. Featured: a multi-policy load balancer with a UVM scoreboard, 17 VC Formal proofs, and a bug-injection matrix.

Parameterized 32-point Radix-2 DIF pipelined FFT coprocessor with AHB-Lite slave interface, and dual-clock async FIFOs. Features an IEEE 1800.2 UVM 1.2 verification suite with C++ DPI-C reference model, RAL, and 100% functional/assertion coverage closure. Targeted for ASIC & FPGA.

AXI4 SRAM controller verification environment using SystemVerilog, UVM-lite, SVA, constrained-random testing, and functional coverage.

An I2C master and the verification environment that proves the testbench itself works - 38 injected RTL defects, 36 killed, both survivors proved rather than excused.