sram

SPI slave to External SRAM interface for Cmod A7

SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.

The code for the ARM processor with forwarding and SRAM, and the synthesized code for implementation on EP2C70F672C8N FPGA board programmed through Quartus II.

SRAM subsystem verification using SystemVerilog UVM, SVA assertions, scoreboard, functional coverage, and 20-seed QuestaSim regression evidence from EDA Playground.

A SystemVerilog implementation of an AXI4-Lite to SRAM controller.

sram自己写的不是mc生成的

Verilog RTL Design and SystemVerilog Verification Projects demonstrating digital design, FSM development, FIFO design, CDC techniques, assertions, and testbench development.

32x8 SRAM with an MBIST controller running MATS+ and March C- against six runtime-injected fault models - including a coupling fault that MATS+ misses and March C- catches.

SRAM memory controller

uvm Axi sram tb

Design of a Single Cycle RISC-V Processor Semester 241 - Computer Architecture

Using Altera FPGA (DE2-115) to finish 3 labs and 1 final project

Analytical simulator for SRMIC — a residency-first LLM inference accelerator architecture using distributed on-package SRAM (HRM) to reduce HBM pressure on the decode critical path.