processor-architecture

5-stage mips processor unicen.

This is a Single Cycle RISC-V processor implemented in verilog

A structural processor design based on the RISC-V ISA, implemented in Verilog. Features both a baseline single-cycle sequential processor and an optimized 5-stage pipelined architecture with robust hazard mitigation. Executes fundamental arithmetic, logical, memory, and branching instructions, verified through comprehensive GTKWave simulations.

Explored x86 assembly programming using NASM, dived into low-level coding and discovered the inner workings of computer hardware and software.

Interview-notes on aspects of Computer Systems.

RISC22 is a simple 22-bit RISC CPU designed in VHDL, featuring a minimal instruction set and a pipelined architecture for efficient execution.

C++ based simulator for different processor designs

Laboratórios da disciplina de Organização e Arquitetura de Computadores, ofertada na Universidade de Brasília (UnB) no semestre de 2021.2.

A MIPS Processor Based on Tomasulo Algorithm

Implementation of the processor model

Une implémentation très simpliste d'un compilateur de code C et d'un microprocesseur associé

Warehouse developed for the hypothetical processor Ramses.

Design and implementaion of a RISC-V processor

The project consists of designing a processor in LogiSim that implements the S-MIPSv2 (Simplified-MIPS Version 2) instruction set architecture.

Course assignments of COL216:- Computer Architecture course at IIT Delhi under Professor Kolin Paul

Assembler for RISC-V instructions

Repository for the course project done as part of CS-230 (Digital Logic Design & Computer Architecture) course at IIT Bombay in Spring 2022.

A server ecosystem

Implementation of Tomasulo's algorithm in Verilog for the Computer Architecture and Design II discipline

General-purpose processor with a 16-bit address & 32-bit data bus