multiplexer

Attach/detach your server application to muxify

SSTP / HTTP Multiplexer

High-performance OS kernel I/O multiplexing (epoll, WSAPoll, kqueue) and asynchronous event engine for Alya

Tiny go package providing a minimal functionality mux that wraps around the go default http.ServeMux. Simplify and enhance the setup of the go http.ServeMux.

A lightweight Telnet proxy that multiplexes a single remote session across multiple local clients for collaboration, monitoring, and debugging.

A digital logic design project implementing an 8x1 Multiplexer (MUX) using basic logic gates. Includes Boolean equations, truth tables, and circuit simulations designed in Logisim.

Your terminal, in formation — a tiling terminal multiplexer for Windows that arranges real Windows Terminal panes around a command center and gives AI agent panes a shared MCP radio to talk, spawn, and coordinate.

Agent MUltipleXer -- drive Claude Code and Codex TUIs programmatically through tmux

Tmux configuration with smart keybindings and session management

5-bit Universal Shift Register digital circuit simulation built in Logisim. Demonstrates parallel load, shift-left, shift-right, and hold operating modes.

TLS multiplexer that routes SSH and HTTP(S) to separate backends on a single port

Network Programming

Multiplexador, proxy reverso e roteador inteligente de cotas para o Google AI Studio Free Tier (Gemini 3.5 / 3.7)

Process Supervisor, Terminal Multiplexer & System Daemon in Rust (Async Tokio, PTY, Systemd & Zeroize Security)

Go library for multiplexing logical streams over a single WebSocket connection. Provides TCP-like semantics (half-close EOF, per-channel flow control) via a clean io.Reader/io.Writer interface. Built on gorilla/websocket.

wumx — Windows terminal multiplexer for AI coding agents

A collection of Digital Logic Design circuits implemented in Verilog HDL, including basic logic gates, adders, and multiplexers with simulation testbenches.

A lightweight TCP multiplexer that accepts incoming client connections and broadcasts their data to multiple backend servers. Written in Elixir for high performance and reliability.

Gate-level implementation of a 2-to-1 multiplexer using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.

This repository contains the Verilog design and testbench for a 8x1 Multiplexer. It uses three select lines to choose one of the eight inputs (A0–A7) and drive it to a single output based on the logic expression: Y = S2'S1'S0'A0 + S2'S1'S0A1 + S2'S1S0'A2 + S2'S1S0A3 + S2S1'S0'A4 + S2S1'S0A5 + S2S1S0'A6 + S2S1S0A7