CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects
Single-Cycle RISC-V Processor in systemverylog
A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL
Getting started with SystemVerilog: Hardware Description Language for design and verification.
simple read/write pcap tasks for SystemVerilog test
Learn independent UVM checking with APB-UART, async FIFOs, and reproducible fault-injection examples.
Pipelined RISC V 32 bit CPU in SystemVerilog
CAPIPrecis a Coherent Accelerator Processor Interface (CAPI) Abstract Layer
SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.
A multi-cycle processor of a cpu designed according to the instruction set (assembly language) of RISC-V using System Verilog HDL.
Pipeline Processor based on RISC-V, implemented forwarding and hazard detection units
This project was a nice idea I had to build a digital logic clock on the DE1-SOC FPGA, while practicing System-verilog, Asynchronous design, and advanced debugging techniques
Quantized neural network inference on FPGA with UART interface and SystemVerilog RTL.
Scrolling Display Implemented With Digital Design Concepts on De1-SoC
Repository of homeworks and projects of the verification class from Bootcamp Pre-Silicon at ITESO with INTEL
Projeto da disciplina de Infraestrutura de Hardware onde o objetivo é criar um pipeline completo e implementação de instruções no processador RISC-V.
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