metastability

Boundary Information Geometry (BIG): reduced mathematical models and prospective numerical tests of system-dependent boundary geometry, response, history, branch structure, reconfiguration, and limits of quantitative transfer.

This is a vhdl implementation of a toggle-level handshake for clock crossing domains.

GEM-Standalone (GEMS3K) Solver of Chemical Equilibria for Coupled Simulation Codes

GEM-Selektor graphical user interface (GEMSGUI)

Clock-domain-crossing verification: a dual-clock asynchronous FIFO with Gray pointers and 2-flop synchronizers, checked across two independent clocks with cocotb. Verified on Icarus Verilog.

Gray-pointer asynchronous FIFO with two-flop synchronisers, verified against unrelated clocks and a behavioural metastability model that the binary-pointer version fails.

Tiny Tapeout TTSKY26c (sky130A): on-chip metastability characterizer -- ring-osc async data + 41-tap delay line + dual-sample witness FFs; raw UART stream for tau/W and MTBF extraction

A mathematical framework for measuring the dynamics of consciousness. The framework uses a composite index of scale-free temporal organisation, cross-frequency organisation, and metastability.

Flip flop setup, hold & metastability explorer tool

NFI integrating mirror layer — cross-domain γ-scaling coherence diagnostics: bootstrap CI, Granger causality, anomaly isolation, phase portraits, reflexive modulation. Single file. Four subsystems. Seven mechanisms.

Hardware-constrained validation of SRFM metastable structural diagnostics on IBM Quantum systems.

SRFM Quantum Phase15: Adaptive Structural Survival Metrics and Metastable Basin Dynamics

Adaptive basin geometry, metastable topology-memory basins, and perturbation-driven structural memory dynamics in SRFM Quantum systems.

SRFM Quantum Phase13: Adaptive Transport Phase Memory and Persistent Topology-Only Structural Memory

Parameterized asynchronous FIFO in Verilog using Gray-coded pointers and 2-stage synchronizers for reliable clock domain crossing, with Full, Empty, Almost-Full and Almost-Empty flags.

Asynchronous FIFO with CDC Reliability Analyzer built from scratch in Verilog. Gray-code pointers, 2-FF synchronizers, randomized stress testbench, timing closure on Artix-7 (WNS = +6.31 ns). No IP cores used.

Asynchronous FIFO design and verification in SystemVerilog based on Clifford Cummings’ “Simulation and Synthesis Techniques for Asynchronous FIFO Design,” using Gray code pointers that are synchronized into a different clock domain before testing for FIFO full or FIFO empty conditions.

Hardware button debouncer with metastability protection - VHDL synchronizer chains and CDC fundamentals for reliable input handling

Hardware button debouncer with metastability protection - VHDL synchronizer chains and CDC fundamentals for reliable input handling

Production-ready asynchronous FIFO buffer with independent read/write clock domains for safe CDC operations. Features Gray code pointers, dual flip-flop synchronizers, metastability prevention, and parameterized design. Essential for SoC inter-module communication and multi-clock systems.