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ila

Here are 11 public repositories matching this topic...

ILAng

PrincetonUniversity / ILAng

A Modeling and Verification Platform for SoCs using ILAs

accelerator verification abstraction ila heterogeneous system-on-chip formal ilang

Updated Jul 3, 2024
C++

PrincetonUniversity / IMDb-Archive

ILA Model Database

modeling verification ila formal

Updated Sep 27, 2020
C++

Nacholazabal / fpga-claude

CLI + Claude Code skill to capture and analyze Vivado ILA waveforms without leaving your editor

embedded fpga xilinx vivado ila vitis claude-ai claude-code claude-skills

Updated Mar 31, 2026
Python

PrincetonUniversity / ItSy

ILA template-based Synthesis

python synthesis ila

Updated Jun 10, 2020
C++

Bo-Yuan-Huang / garnet-ila

The ILA model of the garnet design from Stanford AHA

ila cgra ilang

Updated Jan 10, 2020
Verilog

qinpia59-FX / ADC_Analyze

Windows offline analyzer for FPGA ILA and ADC CSV/TXT/DAT data.

windows fpga adc fft ila signal-analysis dnl inl

Updated Jul 9, 2026

Bo-Yuan-Huang / lmac-ila

ILA of LMAC

ethernet ila formal-specification

Updated Jun 20, 2019
C++

zhanghongce / ila-mcm-fmcad18

ila formal-verification memory-consistency

Updated Aug 23, 2018
Python

DevMajed / FPGA-Carry-Chain-Delay-Line-Capture

256-tap FPGA carry-chain delay-line capture on Basys 3 (Artix-7), built in SystemVerilog with Vivado ILA hardware debugging and raw-pattern visualization.

fpga vivado systemverilog ila basys3 tdc artix-7 carry-chain

Updated Oct 3, 2026
Tcl

DragYin / ebaz4205-counter-ila-vivado

Vivado 2025.1 EBAZ4205 8-bit counter demo using SystemVerilog, Block Diagram, VIO and ILA

fpga zynq vivado systemverilog ila vio ebaz4205

Updated Jul 28, 2026
Tcl

ra9fael / hextract

hextract: A Format-driven decoder for hex word dumps

hex fpga binary dump binary-analysis ila

Updated Aug 26, 2026
Python

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