ece

Ziyuan Chen, ECE411 @ UIUC 23FA

A collection of Verilog HDL projects developed to practice digital design and RTL development concepts, including combinational logic, sequential logic, FSMs, counters, registers, and arithmetic circuits.

Made in the course ECEE402, using Xilinx Vivado 2023.1, BeginDeveloped as part of the ECEE402 course, this project was implemented using Xilinx Vivado 2023.1. It represents foundational work completed during the third year of an undergraduate degree in Electronics Engineering (ECE).ner Work made during my 3rd year ECE undergraduate degree

A Verilog HDL project for an Elevator Control System, complete with a Python Tkinter GUI for real-time simulation. 🚀

Hardware neuron PE in Verilog - MAC engine with sigmoid/ReLU activation for neural network accelerator

A simple UART Transmitter built in Verilog using FSM and tested with Icarus Verilog + GTKWave.

FPGA: serial transmitter sends bitstream, receiver detects 9-bit birthday pattern and displays count on 7-segment display

A 4-bit Arithmetic Logic Unit (ALU) implemented in Verilog HDL with Carry, Zero, Overflow, and Negative status flags. Verified using EDA Playground and EPWave.

Calculator ALU using Verilog HDL with gate-level implementations of logic gates, adders, subtractors, and multiplier.

5-Stage Pipelined RISC Processor implemented in Verilog HDL using Xilinx Vivado with IF/ID, ID/EX, EX/MEM and MEM/WB pipeline registers, RTL simulation and waveform verification

ECE333 Digital Systems Lab coursework with Verilog FPGA designs for UART, VGA graphics, SPI accelerometer interfacing, and an accelerometer-controlled VGA demo on the Nexys A7.

Files regarding synthesis and floorplanning of a RISC V proccessor, using Cadence Genus and Innovus. Project is part of class Digital VLSI-ASIC Design, 9th semester, ECE Aristotle University.

Design and Simulation of a 4-Bit Synchronous Up Counter using Verilog HDL.

RTL implementations of hardware communication protocols in Verilog - UART complete, I2C and SPI planned

Custom 4-bit Processor implemented in Verilog HDL featuring ALU, Register File, Program Counter, Control Unit, Instruction Memory, and simulation in Vivado.

Design and Simulation of a 4-Bit Arithmetic Logic Unit (ALU) using Verilog HDL.

Half Adder implementation using Verilog HDL with testbench, simulation and RTL analysis in Xilinx Vivado.

Verilog HDL practice repository containing combinational, sequential, and behavioural design examples developed during VLSI training, with testbenches, waveforms, and schematics.

32-bit single-cycle MIPS processor in Verilog HDL, synthesizable on Xilinx FPGA

A 4-bit synchronous up counter designed and implemented using Verilog HDL.