cycle-accurate

A cycle-accurate Nintendo Game Boy Advance emulator.

An example of using Ramulator as memory model in a cycle-accurate SystemC Design

NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators

A cycle-accurate microcode-based 8088 emulator for the IBM PC/XT

Development and simulation framework for Application Specific Vector Processor

UniCNet is a cycle-accurate simulator supporting effienct simulation for composable chiplet networks.

Cycle-exact 6502/65C02 CPU emulator core with a stable C ABI and bindings for C++, C#, Java, Python, Rust, JavaScript and WebAssembly.

CAN FD Compliance test suite

An embeddable, clean-room MIT-licensed SNES (5A22 + SPC700) virtual machine, with a source-recovery and decompilation toolchain and a hardware-verified spec.

This is a fork of the Network on Chip Simulator - Noxim, enhanced with the capability to inject traffic traces from multiple in-order processors. The infrastructure and traffic injector can be extended to support more complex processors and traces.

NES emulator

A platform for building, porting, and extending retro games and applications built on the tile-based, indexed-color (CLUT) paradigm, enabling revival and enhancement of existing titles without the original source. Native, cross-platform declarative rendering, virtualization, and co-execution for retro software (Game Boy, SNES, and beyond).

A high-performance, instruction-accurate NES emulator in C++ with 100% nestest compliance, native UI, custom audio filtering, and real-time save states.

Cycle-accurate 5-stage MIPS pipeline simulator in C++ (IF/ID/EX/MEM/WB) with hazard detection + forwarding. Includes per-cycle state tracking and regression tests/traces for correctness.

A T-state accurate, cycle-stepped Intel 8080 emulator written in C++

Headless ares fork for N64 performance work: deterministic, hardware-accurate frame timing from the command line, no console or window needed.

Cycle-accurate Intel 8080 CPU emulator that runs Space Invaders ROM

Comparative benchmark of 6502/65C02 CPU emulation cores across correctness, timing, bus visibility, performance, portability, and integration trade-offs.

Implemented a RISC 5-stage pipeline in C++ and ran a benchmark program to observe a 60% reduction in total execution time between the pipelined and unpipelined design.