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kimdk1005-collab / MimicArm-FPGA-Project

Verilog RTL만으로 구현한 서보 4채널 Teach & Playback 로봇팔 제어기 (Basys3 / Artix-7).

fsm fpga verilog xilinx vivado pwm hdl servo-motor digital-design basys3 robotic-arm artix7 rtl-design teach-and-playback

Updated Aug 10, 2026
Verilog

tangodelta217 / nema-connectome-artix7

Star

Deterministic NEMA v0.1 toolchain for connectome simulation on Artix-7: IR validation, bit-exact fixed-point reference, HLS flow, and reproducible artifacts.

fpga hls verification vivado celegans reproducibility formal-verification connectome artix7

Updated Mar 3, 2026
Python

komihori / XCM-023-100T

Star

fpga artix7 artix-7 fpga-constraints xcm-023-100t xc7a100t xc7a100tfgg484-1

Updated Sep 21, 2024
Tcl

Charith-Mandli / UART-Transmitter-Receiver-Verilog-FPGA

Star

UART Transmitter and Receiver implementation in Verilog HDL with baud rate generation, FSM-based TX/RX architecture, simulation verification, and FPGA implementation on Basys 3 (Artix-7).

fsm fpga embedded-systems verilog uart hardware-designs vlsi digital-design basys3 serial-communication artix7 rtl-design uart-communication xilinxvivado

Updated Jun 16, 2026
Verilog

pushpraj06-Hub / FPGA-Driven-Vertical-Transport-Control-System

Star

FPGA-based multi-floor elevator prototype using Verilog HDL, Vivado, and Xilinx Artix-7 Nexys 4 FPGA Developement Board.

fsm fpga embedded-systems vivado vlsi stepper-motor verilog-hdl digital-design artix7 verilog-project fpga-programming electronics-projects vlsi-project nema-17 elevator-system hardware-project electronics-and-telecommunication lift-system vitpune

Updated Jun 15, 2026

jtgibbs / vivado

Star

Vivado on AWS EC2 — STA, CDC reporting and post-implementation timing simulation, calibrated against a design with known planted bugs

aws fpga verification xilinx vivado artix7 clock-domain-crossing static-timing-analysis

Updated Aug 14, 2026
Tcl

AmberVats / riscv-5stage-core

Star

5-Stage Pipelined RV32IM RISC-V Core with Hazard Forwarding, Dynamic Gshare Predictor, and AXI4-Lite Masters (125 MHz Artix-7).

riscv systemverilog hazard-detection artix7 rv32im axi4-lite pipelined-processor gshare-predictor

Updated Aug 19, 2026
SystemVerilog

deba0272 / NIELIT_VLSI_1_WEEK_TRAINING_PROGRAM

Star

fpga vlsi verilog-hdl xilinx-vivado artix7

Updated Sep 14, 2024

jayjain2365 / 4bit-processor-verilog

Star

4-bit Processor designed in Verilog HDL featuring Fetch, Decode, Execute and Write-Back stages with ALU operations, register file implementation, simulation, and FPGA synthesis using Xilinx Vivado.

fpga verilog xilinx vivado computer-architecture alu vlsi verilog-hdl instruction-set digital-design artix7 processor-design rtl-design hardware-design register-fi

Updated Jun 11, 2026
Verilog

Charith-Mandli / FPGA-Smart-Traffic-Light-Controller

Star

FSM-based Smart Traffic Light Controller implemented in Verilog on Artix-7 FPGA with pedestrian crossing, emergency override, and night mode support.

fsm fpga embedded-systems verilog vivado digital-design traffic-light-controller artix7 hardware-design

Updated May 31, 2026
Verilog

Behagakshay / uart-transceiver-fifo-core

Star

Industrial-grade Full-Duplex UART serial transceiver with 16x oversampling, 2-stage metastability synchronization, and 16-deep synchronous FIFOs in Verilog-2001. Post-route closure at 280 MHz on Xilinx Artix-7 FPGAs.

fpga verilog uart fifo artix7 rtl-design

Updated Jul 1, 2026
Verilog

kimdk1005-collab / EdgeScope-Lite-SoC

Star

Basys3 + MicroBlaze V SoC에 Custom IP 3종을 직접 설계해 구현한 8채널 100 MS/s 하드웨어 로직 애널라이저.

fpga embedded-systems verilog xilinx vivado systemverilog hdl soc logic-analyzer basys3 microblaze artix7 axi4-lite rtl-design vitis

Updated Aug 10, 2026
SystemVerilog

AyushVerma17 / advanced-vending-machine-rtl

Star

Comparative study of Mealy vs Moore FSM architectures in Verilog - Multi-item vending machine controller with timing analysis, and power metrics (79-81.5MHz on Artix-7)

fsm fpga state-machine verilog digital-design xilinx-vivado mealy-machine artix7 moore-machine comparative-study vlsi-design rtl-design hardware-design

Updated Oct 2, 2025
Verilog

aleiei / A7-LITE-xdc

Star

Complete XDC constraints for the MicroPhase A7-LITE FPGA board (DDR3, clock, GPIO, SD, HDMI, Ethernet, QSPI, UART).

fpga constraints xilinx vivado artix7 xdc a7-lite microphase

Updated Aug 12, 2026
Tcl

PreLabHomework / Basys-3-UART-transmitter

Star

This project implements a fully functional UART transmitter that divides the Basys 3's 100 MHz system clock down to a 9600 baud timing reference, builds 10-bit UART frames, and continuously transmits an ASCII message over the onboard USB-UART bridge.

fpga vhdl vivado uart rs232 basys3 artix7

Updated Jun 1, 2026
VHDL

JuanP-G / FPGA-Enigma-Machine

Star

Implementación hardware VHDL de la Máquina Enigma sobre FPGA Artix-7 (Basys 3). Incluye aritmética modular, lógica de rotores electromecánicos y datapath dedicado.

cryptography fpga vhdl vivado enigma-machine basys3 artix7 hardware-design

Updated Feb 6, 2026
VHDL

fanguoc2len / RISC-V-computer

Star

PicoRV32-based mini computer on Basys 3 / Artix-7 with UART, SPI boot, PS/2, VGA text mode, and Vivado regressions

fpga riscv verilog vivado vga basys3 picorv32 artix7

Updated Aug 23, 2026
Verilog

fromabhinavkr / Design-and-Implementation-of-High-Performance-and-Low-Power-RISCV-Processor

Star

This work presents the design and implementation of high performance and low power 32-bit RISC-V processor 4-stage pipelined for non-load and 5-stage for load operations, also extending its capabilities as system on chip (SoC) design. RV32I with M extension designed for FPGA and ASIC

Updated Aug 8, 2026

diegofgcoelho / dct_1d_vhdl

Star

RTL description of 1D DCT using algebraic integers

vhdl rtl dct artix7

Updated Feb 4, 2018
VHDL

ccparke4 / STM32_FPGA_Comm

Star

High-speed heterogeneous computing bridge between STM32H7 and Artix-7 FPGA using SPI and FreeRTOS

spi-interface fpga stm32 freertos spi xilinx systemverilog i2c-bus hardware-acceleration cortex-m7 dma memory-mapped embedded-c artix7 stm32h7 heterogeneous-computing stm32cubeide co-processing

Updated Feb 9, 2026
C

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artix7

Here are 29 public repositories matching this topic...

kimdk1005-collab / MimicArm-FPGA-Project

tangodelta217 / nema-connectome-artix7

komihori / XCM-023-100T

Charith-Mandli / UART-Transmitter-Receiver-Verilog-FPGA

pushpraj06-Hub / FPGA-Driven-Vertical-Transport-Control-System

jtgibbs / vivado

AmberVats / riscv-5stage-core

deba0272 / NIELIT_VLSI_1_WEEK_TRAINING_PROGRAM

jayjain2365 / 4bit-processor-verilog

Charith-Mandli / FPGA-Smart-Traffic-Light-Controller

Behagakshay / uart-transceiver-fifo-core

kimdk1005-collab / EdgeScope-Lite-SoC

AyushVerma17 / advanced-vending-machine-rtl

aleiei / A7-LITE-xdc

PreLabHomework / Basys-3-UART-transmitter

JuanP-G / FPGA-Enigma-Machine

fanguoc2len / RISC-V-computer

fromabhinavkr / Design-and-Implementation-of-High-Performance-and-Low-Power-RISCV-Processor

diegofgcoelho / dct_1d_vhdl

ccparke4 / STM32_FPGA_Comm

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