I verify digital hardware, and my favorite part is chasing a failure down to its root cause. I finished my MS in Electrical and Computer Engineering at Portland State University in June 2026, and I'm looking for entry-level design verification roles in the Bay Area.
| Project | What went wrong | What I did |
|---|---|---|
| Async FIFO CDC (UVM) | Both pointer synchronizers were reset from the source clock domain instead of the destination | Moved each one to its destination-domain reset; the post-fix UVM regression runs 659 writes and 596 reads with 0 mismatches |
| AHB-to-APB bridge (formal) | PSELx paired an undelayed select with a 2-cycle-delayed address, misrouting back-to-back writes | Root-caused it, added matching pipeline registers, and got 3 abandoned properties proving: 44 of 53 proven in VC Formal |
| Load balancer (UVM + formal) | Injected on purpose: the least-loaded policy picks the lowest index instead of the least-loaded backend | Showed the SVA property fails in formal and the scoreboard flags 1,146 mismatches, only in that policy |
| Split L1 cache model (C++20) | A shadowed loop variable sent every instruction-cache lookup to way 0, corrupting MESI state | Fixed it under -Wshadow and locked it in with a 14-trace golden regression |
Each repo opens with a short For reviewers section: what I built, what went wrong, the results, and the limits.
- Checkers stay independent of the design. My scoreboards see only accepted transfers, never DUT internals.
- Every checker has to prove it can fail. I inject bugs and confirm the right assertion or scoreboard catches them.
- I report the gaps. Vacuous properties, missed FSM transitions, and what simulation can't prove go in the README, not under the rug.
SystemVerilog UVM SVA VC Formal QuestaSim Python C++ Tcl Linux Git
LinkedIn · yashaswi.katne99@gmail.com
Outside the lab, you'll find me on a hiking trail or trying a new recipe.