SpecRead: a 385-question benchmark for LLM specification comprehension in hardware design (OpenTitan). v2.1 dataset, sim-verified spec-RTL items, portable eval pipeline.

Hardware Vulnerability Detection Framework Using Large Language Model

A synthesizer capable of transforming SVA properties into synthesizable hardware modules in Verilog register-transfer level (RTL).

Asset Dataset for Crypto, GPIO, and Peripheral IPs using Partial Keyword and Signal Category-based Automatic Tool

This repository contains 4000 vulnerable hardware designs. Currently this is in Jsonl format for directly using it for fine-tuning LLMs. This is open to everyone for use. Thanks!