PTP: ship hardware-timestamped timing engine in v0.1.1 production firmware - #98

Purpose

Promote the already-implemented ARIEC61850/ARSVIN-derived PTP P1/P1.5/P1.75/P2 stack into the normal ARStack Studio / ESP32-P4 production firmware instead of shipping it compiled out.

This does not introduce a second PTP engine. It productizes the existing portable C++ engine, ESP32-P4 IEEE1588 hardware timestamp adapter, measured TIME_RECEIVER discipline path, MONITOR role, and existing Studio PTP Expert controls.

Production v0.1.1 contract

• Studio + firmware version advance to 0.1.1.
• Normal production sdkconfig.defaults enables CONFIG_AR_PTP_LAB_TX=y.
• Default role: LAB_SOURCE.
• Conservative ARSVIN-compatible default profile: domain 0, transportSpecific 0, untagged PTP, Announce 1000 ms, two-step Sync 250 ms, Pdelay response enabled, clockClass 248, unknown accuracy, internal oscillator.
• Semantic device identity and release manifest advertise PTP-P2 + SMPSYNCH-AUTO.
• Studio v0.1.1 fails closed if those production capabilities are absent.
• Normal firmware CI explicitly proves the production PTP-P2 profile is enabled and pulls in portable time-sync changes.
• Dedicated PTP CI continues to build SOURCE and TIME_RECEIVER separately.

Timing architecture retained

• LAB_SOURCE: Announce + hardware-timestamped two-step Sync/Follow_Up + Pdelay response.
• TIME_RECEIVER: hardware RX/TX timestamp correlation, peer-delay, offset measurement, bounded clock discipline, LOCK/HOLDOVER state.
• MONITOR: passive observation.
• PTP remains outside the deterministic SMV CPU1 hot path.

smpSynch truth boundary

PTP packet transmission alone is not a synchronization claim. In LAB_SOURCE / MONITOR, AUTO remains smpSynch=0. Only measured TIME_RECEIVER discipline may promote AUTO to 1/2 under the existing P2 evidence policy. Forced 0/1/2 remain explicit lab stimuli.

Isolation

No apps/ied_simulator/** source or IED Simulator PR branch is changed by this integration. PR #75/#82 remain independent.

Merge gate

1. exact-head firmware + PTP + Studio + release/package CI green;
2. flash the exact v0.1.1 candidate to the ESP32-P4;
3. short physical concurrency check: PTP Announce/Sync/Follow_Up visible and counters progress while SMV remains 4000 fps with zero missed/TX failures;
4. Pdelay response verified when a requester is available;
5. AUTO smpSynch remains truthful.

Physical closeout is deliberately product-focused; this PR does not claim GPS traceability, certified grandmaster behavior, or formal IEEE 1588 / IEC 61850-9-3 conformance.