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Synthesisable Verilog controller for a 700-space university car park: independent occupancy and availability tracking for university and visitor vehicles against one shared capacity, with a transcript-generating testbench and an Intel Quartus project.

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A Time-of-Day Parking Capacity Controller in Verilog

verilog fpga license

A synthesisable parking controller for a 700-space university car park, where capacity is re-partitioned between two classes of vehicle as the day progresses. Built for Digital Systems Design (40223) at Sharif University of Technology, under Dr. Amin Fos'hati.

What makes it more than a counter

A naive design tracks one occupancy number. This one maintains two independent budgets against a single shared physical capacity:

  • 500 spaces are reserved for university-affiliated vehicles.

  • The remainder is available to visitors — but that allowance is not fixed. An on-chip cycle counter divides the day into windows and re-partitions the visitor budget on the boundary:

    Window Visitor spaces
    08:00 – 13:00 200
    13:00 – 16:00 500

The controller therefore has to keep the two occupancy counts, the two remaining-space counts, and the two "is there room?" flags all mutually consistent while the visitor budget shifts underneath them — including the case where the budget shrinks below the number of vehicles already parked.

Interface

module parking_management_system (
    input  wire       clk, reset,
    input  wire       car_entered, car_exited,
    input  wire       is_uni_car_entered, is_uni_car_exited,
    output reg [9:0]  uni_parked_car,    parked_car,
    output reg [9:0]  uni_vacated_space, vacated_space,
    output reg        uni_is_vacated_space, is_vacated_space
);
Signal Direction Meaning
car_entered / car_exited in entry and exit strobes
is_uni_car_entered / is_uni_car_exited in classifies the vehicle on that strobe
uni_parked_car / parked_car out current occupancy, per class
uni_vacated_space / vacated_space out remaining capacity, per class
uni_is_vacated_space / is_vacated_space out room available, per class

Parameters: MAX_PARKING_SPACE = 700, MAX_UNI_SPACE = 500, NON_UNI_BASE_SPACE = 200, CLK_FREQ = 100_000_000.

Layout

src/
  parking_management_system.v      # the design (106 lines)
  tb_parking_management_system.v   # testbench (146 lines)
sim/
  output_results.txt               # full simulation transcript
quartus/
  Parking.qpf / Parking.qsf        # Intel Quartus project + settings
docs/
  report-fa.pdf                    # project report (Persian)

Simulating

The testbench writes its transcript to a file rather than to stdout — it opens output_results.txt in the working directory and $fwrites the full machine state after every event.

With Icarus Verilog:

iverilog -o parking src/parking_management_system.v src/tb_parking_management_system.v
vvp parking          # writes output_results.txt into the current directory

With ModelSim / Questa:

vlog src/parking_management_system.v src/tb_parking_management_system.v
vsim -c TB_parking_management_system -do "run -all; quit"

The testbench drives entry and exit sequences for both vehicle classes and walks the clock across a time-window boundary so the re-partitioning is exercised. sim/output_results.txt is the committed transcript of that run — 4,992 lines of per-event state, so the behaviour can be inspected without a simulator to hand.

That transcript reproduces: a fresh Icarus run emits the same 4,992 lines with identical content (the committed copy carries some leading indentation from the original capture, so compare with whitespace stripped).

Synthesis

Open quartus/Parking.qpf in Intel Quartus Prime, then compile to produce a bitstream for your target device. Build outputs are deliberately not committed.

Report

docs/report-fa.pdf is the project report. It is in Persian.

License

MIT.

About

Synthesisable Verilog controller for a 700-space university car park: independent occupancy and availability tracking for university and visitor vehicles against one shared capacity, with a transcript-generating testbench and an Intel Quartus project.

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84 stars

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