Skip to content

Commit f98d33b

Browse files
aswatermanpalmer-dabbelt
aswaterman
authored and
palmer-dabbelt
committed
Add SFENCE.VMA instruction
include/ChangeLog: 2017-02-14 Andrew Waterman <andrew@sifive.com> * opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define. (MASK_SFENCE_VMA): Likewise. (sfence_vma): Declare instruction. opcodes/ChangeLog: 2017-02-14 Andrew Waterman <andrew@sifive.com> * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and pseudoinstructions.
1 parent 773fb66 commit f98d33b

4 files changed

Lines changed: 17 additions & 0 deletions

File tree

‎include/ChangeLog‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,9 @@
1+
2017-02-14 Andrew Waterman <andrew@sifive.com>
2+
3+
* opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define.
4+
(MASK_SFENCE_VMA): Likewise.
5+
(sfence_vma): Declare instruction.
6+
17
2017-02-14 Alan Modra <amodra@gmail.com>
28

39
PR 21118

‎include/opcode/riscv-opc.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -227,6 +227,8 @@
227227
#define MASK_DRET 0xffffffff
228228
#define MATCH_SFENCE_VM 0x10400073
229229
#define MASK_SFENCE_VM 0xfff07fff
230+
#define MATCH_SFENCE_VMA 0x12000073
231+
#define MASK_SFENCE_VMA 0xfe007fff
230232
#define MATCH_WFI 0x10500073
231233
#define MASK_WFI 0xffffffff
232234
#define MATCH_CSRRW 0x1073
@@ -883,6 +885,7 @@ DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
883885
DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
884886
DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
885887
DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
888+
DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
886889
DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
887890
DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
888891
DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)

‎opcodes/ChangeLog‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,8 @@
1+
2017-02-14 Andrew Waterman <andrew@sifive.com>
2+
3+
* riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
4+
pseudoinstructions.
5+
16
2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
27

38
* aarch64-opc.c (aarch64_sys_regs): Add SVE registers.

‎opcodes/riscv-opc.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -678,6 +678,9 @@ const struct riscv_opcode riscv_opcodes[] =
678678
{"dret", "I", "", MATCH_DRET, MASK_DRET, match_opcode, 0 },
679679
{"sfence.vm", "I", "", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 },
680680
{"sfence.vm", "I", "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 },
681+
{"sfence.vma","I", "", MATCH_SFENCE_VMA, MASK_SFENCE_VMA | MASK_RS1 | MASK_RS2, match_opcode, INSN_ALIAS },
682+
{"sfence.vma","I", "s", MATCH_SFENCE_VMA, MASK_SFENCE_VMA | MASK_RS2, match_opcode, INSN_ALIAS },
683+
{"sfence.vma","I", "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
681684
{"wfi", "I", "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
682685

683686
/* Terminate the list. */

0 commit comments

Comments
 (0)