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A FlatSat board designed to dock 4 PC104 Modules for testing and debugging. The board will be produced by JLCPCB, so it complies to JLCPCB's capabilities listed on their website.
The board was designed with the pinout followed by SatNOGS COMMS in mind. More about this pinout can be found here. All 104 pins of each module are connected to all 104 pins of the other modules, so problems when using a different pinout can only arise if power nets are assigned to different pins on your pinout.
This FlatSat is a 4-layer board with GND and routed power on the top and bottom layers and signals routed on the inner layers to increase EMI immunity. When routing power, care was taken not to intercept the signals' return paths. Moreover, traces on the 2 inner layers were routed perpendicular to each other which helps reduce capacitive crosstalk. For the same cause, we chose to use JLC3313 stackup which provides larger distance between the inner layers (thus less capacitive coupling) as well as shorter distance from the top and bottom to the inner layers (so fields generated by the traces on the inner layers are less spread) compared to the JLC7628 stackup.
A 2mm trace width was chosen for the power rails on the outer layer, which is sufficient for 5.3A with a 20°C temperature rise.
Long traces on the FlatSat do not resemble the much more direct connection on a vertical bus, both in terms of crosstalk and in terms of losses. Whether signals can be properly transmitted through the FlatSat has not been tested yet.
With so many signals closely packed, increased crosstalk is anticipated. Traces assigned to SPI and I2C nets were routed with as much clearance as possible from the nearby traces (which are not used in SatNOGS COMMS). CAN traces had to be length-matched, so they were peripherally routed.
Power is provided through banana terminals, that are capable of high amperage. No advanced protection measured are present on the board, just a reverse polarity protection mechanism. With regard to overcurrent protection, we rely on the current limiter on the bench power supply.
In order to reduce board dimensions and cost, FlatSat is designed in a way that only the PC104 connector and 2 mounting holes from each module are connected to it. So, a kind of 3d printed or metal base will be required to establish a sturdy mechanical setup. Modules connected on the FlatSat were considered to follow the LibreCube mechanical format, which practically affects mounting hole positions.
Expansion Together with the FlatSat, a PC104 bridge board was designed. This board allows up to 3 FlatSat boards to be connected in order to increase total capacity. Summarized below are the 3 use cases of the 2 boards :
| Components | PC104 module capacity |
|---|---|
| FlatSat | 4 |
| 2xFlatSat + bridge | 7 |
| 3xFlatSat + 2xbridge | 10 |
When connecting more than one FlatSat boards, the PC104 bridge boards connect to the PC104 slots on the top left or top right side of the board (those near the banana sockets) and then another FlatSat connects to the bridge after it has been rotated by 90° clockwise or counter-clockwise respectively. Top view and isometric view of 3 FlatSat boards assembled this way are shown below.
Ease of use
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CAN_A and CAN_B busses are broken out (together with 5V and GND) into Molex PicoBlade connectors.
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Silkscreen placeholders to write details about each system have been placed.
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Power and communication lines (according to SatNOGS COMMS pinout) can be disconnected for each module by a 2.54mm shunt jumper (not shown on the images above). This addition required sacrifices to be made in terms of interrupting some signal's return paths.
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5V on the CANBUS breakout connectors are supplied via an LM1117 LDO, while a thick trace has been routed in the PC104 pin that some LibreCube use for 5V power. The two nets are not connected.
One FlatSat and 2 PC104 bridge boards can be ordered together as a panel.
The following signal integrity parameters are tested :
- Signal deformation (smooth edges instead of a square pulse)
- Crosstalk
- Ringing on the rising / falling edge
- Signal phase lag
Tests were performed using either a MHS-5200A dual channel signal generator and a RIGOL DS4024 digital oscilloscope as a measurement tool.
Regarding the location of the modules on the board, one can locate six PC/104 connectors. Starting from the one on the most left side of the board and moving clockwise, they are logically labeled as CL,TL,TR,CR,BR,BL (center left, top left, etc.).
When connected on the FlatSat, the signal generator had a realtively slow rise time of 20ns. As a measure of comparison, a PWM signal generated from an STM32F103 Nucleo board had a 7ns rise time. However, the same Nucleo board also had a rise time of about 20ns when connected on the FlatSat, so it is more probable that the parasitic elements of the board increase the rise time of the signal (a higher current driver would be required for a smaller rise time).
The signal generator probe is placed on pin 45 of one of the PC/104 connectors. One oscilloscope channel (CH1) is placed on the same pin to measure the undistorted signal. Both probes are grounded on pins 33 and/or 34. Another oscilloscope channel (CH2) is placed on pin 45 of another PC/104 connector, and is grounded on pin 33 or 34 of said connector. The measurements from CH1 and CH2 are compared.
- Signal rise time : (measured) 20ns
- Peak to peak signal voltage : 5V
- Test frequency : 2MHz. Signal generator was producing poor square pulses above that frequency. However, the 2 measured signals exhibited the same behavior on 2-4-5 MHz frequencies, regardless of the fact that they were both degraded squares in the first place.
- Signal was injected from the CL connector, and output was measured on the CR connector, since these were the connectors with the largest distance between them.
As one can see from the oscilloscope screenshot below, there was indistinguishable signal distortion, ringing, or phase lag between the input and the output signal. Always keep the test conditions in mind when interpreting the test results. On the piscture below, the yellow trace is the input signal and the blue trace corresponds to the output.
The signal generator probe is placed on pin 45 of one of the PC/104 connectors. One oscilloscope channel (CH1) is placed on the same pin to measure the aggressor's signal. Both probes are grounded on pins 33 and/or 34. Another oscilloscope channel (CH2) is placed on pin 47 of another PC/104 connector, and is grounded on pin 33 or 34 of said connector. CH2 peak-to-peak voltage was the measured quantity.
- Aggressor : H1_45
- Victim : H1_47
The oscilloscope probe measured 60mV peak-to-peak when resting on the table, without any signal.
- Signal rise time : (measured) 20ns
- Peak to peak signal voltage : 5V
- Test frequency : 2MHz
Output crosstalk was measured with the output probe positioned on the CR and BL modules to confirm that larger length of closely-spaced conductors leads to larger crosstalk. Keep in mind that the signal was 5V peak-to-peak and that the rise time was not a particuraly fast one.
On the CR connector
On the BL connector
Indeed, crosstalk on the CR connector is larger than the BL connnector. Regarding the crosstalk magnitude, one should consider the idle state "crosstalk" (~60mV) when interpreting the results.