Electronics and Instrumentation Engineering graduate (2026) with a focus on VLSI, CMOS and mixed-signal IC design, RTL, and semiconductor technology.
I am interested in understanding electronic systems from the transistor level to system implementation, with hands-on experience in custom CMOS design, digital hardware, FPGA systems, and semiconductor device simulation.
- VLSI & CMOS Design
- Analog & Mixed-Signal IC Design
- RTL Design & FPGA
- Semiconductor Device Simulation & TCAD
- Physical Design & Silicon Validation
Designed and analyzed a 12-bit asynchronous SAR ADC architecture, including the CDAC, StrongARM comparator, TSPC-based SAR logic, and asynchronous clock generation.
Designed and characterized a full-custom TSPC D flip-flop through schematic, layout, DRC/LVS, parasitic extraction, timing, power, and PVT analysis.
Designed and compared static and dynamic D flip-flop architectures with emphasis on timing and power characteristics.
Implemented Verilog-based digital systems on FPGA using Xilinx Vivado, covering RTL development, simulation, synthesis, timing verification, and hardware testing.
ISWDP Samsung Fellow — Grade II
Semiconductor workforce training through the IISc-led ecosystem, with exposure to:
- Semiconductor device physics
- TCAD workflows
- Device structure creation
- Device simulation and modeling
- Device analysis
Also completed VLSI training in Analog and Digital VLSI at IIT Kharagpur.
VLSI: LTspice · Electric VLSI · TCAD
HDL & FPGA: Verilog · Xilinx Vivado · ZedBoard
Simulation: MATLAB · Simulink · Ngspice
Programming: C · C++
Systems: Linux · Git · ArduPilot · MAVLink · SITL/HIL
I am open to learning from and connecting with professionals, researchers, and engineers working in VLSI, semiconductor design, CMOS, mixed-signal ICs, RTL, and related areas.