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[MLIR] tbb fixes #189

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Hardcode84 merged 4 commits into from
Feb 23, 2021
Merged

[MLIR] tbb fixes #189

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805e06e
fix plier parallel
Feb 20, 2021
684e897
use loop to init reduce vars
Feb 20, 2021
40ce8c5
transfor to tbb parallel if have parallel attr or outermost loop
Feb 20, 2021
b72ddff
we dont need fix_tls_observer, also do not recreate task arena each time
Feb 20, 2021
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fix plier parallel
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Butygin
Butygin committed Feb 23, 2021
commit 805e06e0dfcc3217ee5714f213f097dc4a64611a
6 changes: 4 additions & 2 deletions mlir-compiler/mlir-compiler/src/pipelines/parallel_to_tbb.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -86,7 +86,6 @@ struct ParallelToTbb : public mlir::OpRewritePattern<mlir::scf::ParallelOp>
auto index = static_cast<unsigned>(it.index());
reduce_vars[index] = reduce;
auto zero = getZeroVal(rewriter, loc, type);
mapping.map(op.initVals()[index], zero);
for (unsigned i = 0; i < max_concurrency; ++i)
{
mlir::Value index = rewriter.create<mlir::ConstantIndexOp>(loc, i);
Expand All @@ -100,16 +99,19 @@ struct ParallelToTbb : public mlir::OpRewritePattern<mlir::scf::ParallelOp>
auto orig_step = op.step().front();
auto body_builder = [&](mlir::OpBuilder &builder, ::mlir::Location loc, mlir::Value lower_bound, mlir::Value upper_bound, mlir::Value thread_index)
{
llvm::SmallVector<mlir::Value, 8> initVals(op.initVals().size());
for (auto it : llvm::enumerate(op.initVals()))
{
auto reduce_var = reduce_vars[it.index()];
auto val = builder.create<mlir::LoadOp>(loc, reduce_var, thread_index);
mapping.map(it.value(), val);
initVals[it.index()] = val;
}
auto new_op = mlir::cast<mlir::scf::ParallelOp>(builder.clone(*op, mapping));
new_op->removeAttr(plier::attributes::getParallelName());
assert(new_op->getNumResults() == reduce_vars.size());
new_op.lowerBoundMutable().assign(lower_bound);
new_op.upperBoundMutable().assign(upper_bound);
new_op.initValsMutable().assign(initVals);
for (auto it : llvm::enumerate(new_op->getResults()))
{
auto reduce_var = reduce_vars[it.index()];
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