Tirthajyoti Sarkar

Fremont, California, United States
18K followers 500+ connections

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About

Building Digital Nervous Systems with Data, AI, and Math.

Large software systems…

Experience & Education

  • Rhombus Power Inc.

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Volunteer Experience

  • Track chair, AI Optimization, AI Expo 2021

    ValleyML

    - Present 5 years 7 months

    Science and Technology

    Track chair for the "AI Optimization" track in the AI Expo, 2021.

  • Content Committee Member

    Open Data Science Conference (ODSC)

    - Present 6 years 5 months

    Science and Technology

    Reviewing content, proposing speaker line-up, and providing feedback to the organizing committee for the ODSC West 2020 conference.

  • Committee Member, AI Expo, 2020

    ValleyML

    - Present 6 years 3 months

    Science and Technology

    Committee member for the AI Expo 2020. Link here: https://www.valleyml.ai/

  • Co-chair of Semiconductor Committee

    PSMA (Power Sources Manufacturers Association)

    - Present 7 years 8 months

    Science and Technology

    Co-chairing the semiconductor committee of PSMA. Responsibilities include, (a) Arranging semiconductor-related industry sessions at APEC conference, (b) arranging regular webinars related to power semiconductor technology, (c) formulating research projects proposal.

  • Editorial associate

    Towards Data Science

    - 1 year 1 month

    Science and Technology

    I served as Editorial Associate for the highly popular online Publication Towards Data Science. My responsibilities and goals are as follows,
    - Find excellent content and great authors who write about data science and related topics.
    - Provide feedback to promising writers about style, content, and presentation.
    - Network with experts in industry and research.

  • Industry Expert (Wide and narrow bandgap semiconductors), IEEE Power Electronics Society (PELS)

    IEEE

    - Present 9 years 8 months

    Science and Technology

    Serving in the 'industry expert' role for IEEE Power Electronics Society, Technical Committee-5 (TC-5) in the Thrust area of wide and narrow bandgap technologies for sustainable energy systems.

  • Topic Chair for IEEE ECCE Conference (2016, 2017,2018) - Renewable and Alternative Energy Track

    IEEE

    - Present 9 years 11 months

    Science and Technology

    I am serving a Topic Chair for Sustainable Energy Track in IEEE ECCE Conference. Responsibilities include of working together with other chairs to hand pick proper reviewers for each submitted paper, judge the merit of the peer review, and if deemed publication-worthy, integrate the paper into suitable niche of the whole conference/technical program.

  • Technical Track Chair - International Transportation Electrification Conference (India), 2017

    IEEE

    - Present 9 years 8 months

    Science and Technology

    I have been drafted in the Program Committee of International Transportation Electrification Conference (ITEC) India, 2017. It will be in Pune in Dec 2017.

    If you have publishable work on Electric Vehicle and general electronic systems/motor drives in automobiles, aircraft or naval transports (personal, commercial, military, off-road anything), please consider showcasing your work.

  • Technical Program Committee member, PICC2018

    IEEE

    - Present 9 years

    Science and Technology

    Technical Program Committee member for the International Conference on Power Electronics, Instrumentation, Control and Computing (PICC2018). The conference is intended to be a forum for technical exchange among researchers from academia, research groups, and industries in the emerging fields of Power Electronics, Power Systems, Control and Instrumentation as applied to power electronics/systems. More details of the conference is available the conference website:…

    Technical Program Committee member for the International Conference on Power Electronics, Instrumentation, Control and Computing (PICC2018). The conference is intended to be a forum for technical exchange among researchers from academia, research groups, and industries in the emerging fields of Power Electronics, Power Systems, Control and Instrumentation as applied to power electronics/systems. More details of the conference is available the conference website: http://icetest.gectcr.ac.in/electrical/

  • Roadmap development activity for low-voltage FET technology

    PSMA (Power Sources Manufacturers Association)

    - 3 months

    Science and Technology

    Contributing to the PSMA Annual Roadmap development document in the category of Low-voltage power device technology. Writing about low-voltage power MOSFET technology progression, key figures-of-merit, application trends, and emerging challenges.

  • Technical Track Chair, IEEE Power Electronics, Drives and Energy Systems Conference

    IEEE

    - 11 months

    Science and Technology

    I am serving as Technical Track Chair for the Power Device, Packaging, EMI track for IEEE PEDES conference. Responsibilities include collaboration with fellow researchers to hand pick proper reviewers for each submitted paper, judge the merit of the peer review, and if deemed publication-worthy, integrate the paper into suitable niche of the whole conference/technical program.

    Visit: http://www.pedes2016.org/

  • Power Electronics Devices and Components Committee - IEEE Industry Application Society (IAS)

    IEEE

    - Present 10 years 2 months

    Science and Technology

    The Power Electronics Devices and Components Committee is responsible for all matters within the scope of the IAS in which the emphasis or dominant factor specifically relates to power electronics devices and components and their applications. I am a member.

    https://www.linkedin.com/groups/2983007

Patents

  • Optically-triggered multi-stage power system and devices

    Issued US 8,294,078

    A multi-stage optically-triggered power system. At least one triggering stage is responsive to at least one optical trigger to directly create photogeneration of carriers in the at least one triggering stage and thus generate at least one output signal. At least one main power device stage coupled to the at least one triggering stage is responsive to the at least one generated output signal to activate the at least one main power device stage. The at least one triggering stage and the at least…

    A multi-stage optically-triggered power system. At least one triggering stage is responsive to at least one optical trigger to directly create photogeneration of carriers in the at least one triggering stage and thus generate at least one output signal. At least one main power device stage coupled to the at least one triggering stage is responsive to the at least one generated output signal to activate the at least one main power device stage. The at least one triggering stage and the at least one main power device stage may be monolithically integrated.

    Other inventors
    See patent
  • Optically Triggered Power System and Devices

    Issued US 8,183,512

    A power device is provided in an optically-triggered power system having a controller for generating electrical control signals and a converter for converting the electrical control signals to optical control signals. The power device includes a pair of terminals and a P-body region provided adjacent an N+ source region. An optical window is provided at least partially over the P-body region, and an N− drift region is provided between the two terminals. The P-body region causes current to…

    A power device is provided in an optically-triggered power system having a controller for generating electrical control signals and a converter for converting the electrical control signals to optical control signals. The power device includes a pair of terminals and a P-body region provided adjacent an N+ source region. An optical window is provided at least partially over the P-body region, and an N− drift region is provided between the two terminals. The P-body region causes current to conduct between the first and second terminal through the N− drift region when an optical control signal is incident on the optical window.

    Other inventors
    See patent
  • FAST AND STABLE ULTRA LOW DROP-OUT (LDO) VOLTAGE CLAMP DEVICE

    Filed US US 2016/0079230 A1

    An integrated circuit (e.g., a downstream integrated circuit) can be protected from undesirable power conditions (e.g., overvoltage conditions, overcurrent condition) using a protection device. The protection device, however, may not be configured to provide protection in response to each of the various types of undesirable power conditions that can occur such as a current in-rush upon activation, a current surge, and/or so forth. Accordingly, the protection device selected for power protection…

    An integrated circuit (e.g., a downstream integrated circuit) can be protected from undesirable power conditions (e.g., overvoltage conditions, overcurrent condition) using a protection device. The protection device, however, may not be configured to provide protection in response to each of the various types of undesirable power conditions that can occur such as a current in-rush upon activation, a current surge, and/or so forth. Accordingly, the protection device selected for power protection may not provide adequate protection of the integrated circuit or associated components in a desirable fashion. In addition, other components included in the integrated circuit may be increased in size to compensate for the inadequacies of the protection device in response to certain types of undesirable power conditions. Thus, a need exists for systems, methods, and apparatus to address the shortfalls of present technology and to provide other new and innovative features.

    In one general aspect, an apparatus can include a junction-less, gate-controlled voltage clamp device having a gate terminal coupled to a voltage reference device.

    The details of one or more implementations are set forth in the accompanying drawings and the description. Other features will be apparent from the description and drawings, and from the claims.

    Other inventors
    See patent
  • JUNCTION-LESS INSULATED GATE CURRENT LIMITER DEVICE

    Filed US 20150043114 A1

    In one general aspect, an apparatus can include a semiconductor substrate, and a trench defined within the semiconductor substrate and having a depth aligned along a vertical axis, a length aligned along a longitudinal axis, and a width aligned along a horizontal axis. The apparatus includes a dielectric disposed within the trench, and an electrode disposed within the dielectric and insulated from the semiconductor substrate by the dielectric. The semiconductor substrate can have a portion…

    In one general aspect, an apparatus can include a semiconductor substrate, and a trench defined within the semiconductor substrate and having a depth aligned along a vertical axis, a length aligned along a longitudinal axis, and a width aligned along a horizontal axis. The apparatus includes a dielectric disposed within the trench, and an electrode disposed within the dielectric and insulated from the semiconductor substrate by the dielectric. The semiconductor substrate can have a portion aligned vertically and adjacent the trench, and the portion of the semiconductor substrate can have a conductivity type that is continuous along an entirety of the depth of the trench. The apparatus is biased to a normally-on state.

    Other inventors
    See patent
  • Methods and apparatus including a current limiter

    Filed EU EP20140000944

    In one general aspect, an apparatus can include a load terminal, and a power source terminal. The apparatus can include a current limiter coupled to the load terminal and coupled to the power terminal. The current limiter can be configured to limit a current from the power source terminal to the load terminal using an electric field activated in response to a difference in voltage between the power source terminal and the load terminal.

    Other inventors
    See patent

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