UMC, a semiconductor foundry, has delivered 65nm FPGAs to Xilinx. This new devices deliver a 65 percent logic capacity increase over previous generation FPGAs to enable the industry's highest gate count, with approximately... |
UMC, a semiconductor foundry, has delivered 65nm FPGAs to Xilinx. This new devices deliver a 65 percent logic capacity increase over previous generation FPGAs to enable the industry's highest gate count, with approximately 1.1 billion transistors, as per a statement issued by the company.
Jackson Hu, chairman and CEO of UMC, said, "UMC's 65nm technology has seen widespread acceptance from manufacturers of cell phones, FPGA, graphics and broadband applications. Particularly noteworthy, is the number of new customers engaged at this technology node."
Wim Roelandts, chairman, president and CEO of Xilinx, said, "Xilinx is currently ramping 65nm wafer starts at UMC. We are quite pleased with our progress-in fact, UMC's yields have exceeded our expectations for our most advanced products. We'll continue to leverage UMC's advanced 65nm technology for our upcoming product lines to strengthen our leading position in the FPGA industry."
Chipworks Evaluates Xilinx Virtex-5 FPGA 65nm "Twins"
Chipworks, a provider of reverse engineering and analysis of semiconductor chips and systems, has analysed twin samples of the Xilinx XC5VLX50 Virtex-5 FPGA, made in a 65nm process.
"Keeping ahead of the competition is as critical to Xilinx as it is to all semiconductor companies," says Terry Ludlow, Chipworks founder and CEO. "The Virtex-5 demonstrates Xilinx use of multiple foundries to expedite 65nm device manufacturing, thus providing them with a hedge against process problems while increasing their volume production capability. In addition, the relationships with Toshiba and UMC ensure that Xilinx remains at the forefront of technology."
Both devices have 12 metal layers (11 copper and one aluminum) and are fabbed from 300 mm wafers. In addition both use tensile nitride strain on NMOS transistors. However, Chipworks analyses have revealed significant differences in the metallisation and dielectric structures. Other differences will be detailed in Chipworks reports on these devices. As these devices ramp into production it will be interesting to note if these differences have an impact on the performance, cost or power consumption of the Virtex-5, the company said.
Chipworks analyses provides intelligence into the structural and process elements Xilinx used to achieve performance improvements with the Virtex-5 while using less power and dropping the cost by 45% from earlier generations. Chipworks customers rely upon this type of information to learn from their competitors, improve their own designs and speed their time-to-market, the company said.
|
