Peter Monsson

@SVAssertions

Debug tips | UVMkit.com | Independent ASIC design and verification Consultant

Copenhagen, Denmark

Peter Monsson
@SVAssertions
Dec 5, 2023
Have you integrated Python into an existing #SystemVerilog #UVM testbench? What is the performance overhead? How do you handle communication? TLM? #Verilog #semiconductor #chipdesign #digitalverification #sv #verification #servingthenextbug
1
Peter Monsson
@SVAssertions
Oct 1, 2023
🔥 #Verification Tip: FSMs are a pain to verify in #SystemVerilog, but this tip makes it easier. Most designers declare their state variables as an typedef'ed enum. Typedefs inside modules are local to the module.
2
Peter Monsson
@SVAssertions
Aug 20, 2023
How I think about #verification techniques Unit testing: For fast and fun verification Formal Verification: For peace of mind #UVM: When the other two fail None of them are better than others. They all have their strengths
Peter Monsson
@SVAssertions
Apr 16, 2023
Debugging with waves in the log: Over the last month I have improved sv_waveterm with: 1. Verilator support 2. A license file 3. Unit tests 4. Continuous Integration 5. Cleaner code 6. Better performance github.com/PeterMonsson/s… 1/2
GitHub - PeterMonsson/sv_waveterm
From github.com
1
Peter Monsson
@SVAssertions
Mar 12, 2023
See waveforms in the log: 1. Packaged sv_waveterm so that it is easier to use 2. Wrote a README for sv_waveterm 3. Uploaded sv_waveterm to github github.com/PeterMonsson/s… Can you use it as it is? Are there hurdles? Looking for your feedback. Thanks!
GitHub - PeterMonsson/sv_waveterm
From github.com