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Merged: [ia32][wasm-simd] Fix aligned moves in codegen
For SIMD instructions that use aligned moves (like movaps or movapd), we don't have correct memory alignment for SIMD moves yet. Switch to to movupd. TBR=bbudge@chromium.org,adamk@chromium.org Bug: v8:9198 Bug: v8:10831 Bug: chromium:1134039 (cherry picked from commit ab23ff3) Change-Id: Icc038b4a32364b8bc66b723403ccc11f954b080d No-Try: true No-Presubmit: true No-Tree-Checks: true Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2469600 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/branch-heads/8.6@{#30} Cr-Branched-From: a64aed2-refs/heads/8.6.395@{#1} Cr-Branched-From: a626bc0-refs/heads/master@{#69472}
1 parent 69eb682 commit ed3eeda

5 files changed

Lines changed: 21 additions & 4 deletions

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‎src/codegen/ia32/assembler-ia32.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -963,6 +963,9 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
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void movapd(XMMRegister dst, Operand src) {
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sse2_instr(dst, src, 0x66, 0x0F, 0x28);
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}
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void movupd(XMMRegister dst, Operand src) {
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sse2_instr(dst, src, 0x66, 0x0F, 0x10);
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}
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void movmskpd(Register dst, XMMRegister src);
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void movmskps(Register dst, XMMRegister src);
@@ -1338,6 +1341,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
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void vmovapd(XMMRegister dst, Operand src) { vpd(0x28, dst, xmm0, src); }
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void vmovups(XMMRegister dst, XMMRegister src) { vmovups(dst, Operand(src)); }
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void vmovups(XMMRegister dst, Operand src) { vps(0x10, dst, xmm0, src); }
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void vmovupd(XMMRegister dst, Operand src) { vpd(0x10, dst, xmm0, src); }
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void vshufps(XMMRegister dst, XMMRegister src1, XMMRegister src2, byte imm8) {
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vshufps(dst, src1, Operand(src2), imm8);
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}

‎src/codegen/ia32/macro-assembler-ia32.h‎

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Original file line numberDiff line numberDiff line change
@@ -294,6 +294,7 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
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AVX_OP2_WITH_TYPE(Movaps, movaps, XMMRegister, XMMRegister)
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AVX_OP2_WITH_TYPE(Movapd, movapd, XMMRegister, XMMRegister)
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AVX_OP2_WITH_TYPE(Movapd, movapd, XMMRegister, const Operand&)
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AVX_OP2_WITH_TYPE(Movupd, movupd, XMMRegister, const Operand&)
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AVX_OP2_WITH_TYPE(Pmovmskb, pmovmskb, Register, XMMRegister)
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AVX_OP2_WITH_TYPE(Movmskps, movmskps, Register, XMMRegister)
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‎src/compiler/backend/ia32/code-generator-ia32.cc‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1968,7 +1968,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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tmp = i.TempSimd128Register(0);
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// The minpd instruction doesn't propagate NaNs and +0's in its first
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// operand. Perform minpd in both orders, merge the resuls, and adjust.
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__ Movapd(tmp, src1);
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__ Movupd(tmp, src1);
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__ Minpd(tmp, tmp, src);
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__ Minpd(dst, src, src1);
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// propagate -0's and NaNs, which may be non-canonical.
@@ -1987,7 +1987,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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tmp = i.TempSimd128Register(0);
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// The maxpd instruction doesn't propagate NaNs and +0's in its first
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// operand. Perform maxpd in both orders, merge the resuls, and adjust.
1990-
__ Movapd(tmp, src1);
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__ Movupd(tmp, src1);
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__ Maxpd(tmp, tmp, src);
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__ Maxpd(dst, src, src1);
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// Find discrepancies.
@@ -2383,7 +2383,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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XMMRegister dst = i.OutputSimd128Register();
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Operand src1 = i.InputOperand(1);
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// See comment above for correction of maxps.
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__ movaps(kScratchDoubleReg, src1);
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__ vmovups(kScratchDoubleReg, src1);
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__ vmaxps(kScratchDoubleReg, kScratchDoubleReg, dst);
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__ vmaxps(dst, dst, src1);
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__ vxorps(dst, dst, kScratchDoubleReg);

‎src/diagnostics/ia32/disasm-ia32.cc‎

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1173,6 +1173,10 @@ int DisassemblerIA32::AVXInstruction(byte* data) {
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int mod, regop, rm, vvvv = vex_vreg();
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get_modrm(*current, &mod, &regop, &rm);
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switch (opcode) {
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case 0x10:
1177+
AppendToBuffer("vmovupd %s,", NameOfXMMRegister(regop));
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current += PrintRightXMMOperand(current);
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break;
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case 0x28:
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AppendToBuffer("vmovapd %s,", NameOfXMMRegister(regop));
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current += PrintRightXMMOperand(current);
@@ -2108,7 +2112,13 @@ int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer,
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data += 2;
21092113
} else if (*data == 0x0F) {
21102114
data++;
2111-
if (*data == 0x28) {
2115+
if (*data == 0x10) {
2116+
data++;
2117+
int mod, regop, rm;
2118+
get_modrm(*data, &mod, &regop, &rm);
2119+
AppendToBuffer("movupd %s,", NameOfXMMRegister(regop));
2120+
data += PrintRightXMMOperand(data);
2121+
} else if (*data == 0x28) {
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data++;
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int mod, regop, rm;
21142124
get_modrm(*data, &mod, &regop, &rm);

‎test/cctest/test-disasm-ia32.cc‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -473,6 +473,7 @@ TEST(DisasmIa320) {
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__ movapd(xmm0, xmm1);
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__ movapd(xmm0, Operand(edx, 4));
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__ movupd(xmm0, Operand(edx, 4));
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__ movd(xmm0, edi);
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__ movd(xmm0, Operand(ebx, ecx, times_4, 10000));
@@ -689,6 +690,7 @@ TEST(DisasmIa320) {
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__ vmovaps(xmm0, xmm1);
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__ vmovapd(xmm0, xmm1);
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__ vmovapd(xmm0, Operand(ebx, ecx, times_4, 10000));
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__ vmovupd(xmm0, Operand(ebx, ecx, times_4, 10000));
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__ vshufps(xmm0, xmm1, xmm2, 3);
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__ vshufps(xmm0, xmm1, Operand(edx, 4), 3);
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__ vhaddps(xmm0, xmm1, xmm2);

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