riscv-arch-test/config/cores/cvw/cvw-rv64gc/cvw-rv64gc.yaml at act4 · riscv/riscv-arch-test

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# yaml-language-server: $schema=https://raw.githubusercontent.com/riscv/riscv-unified-db/main/spec/schemas/config_schema.json

---

$schema: config_schema.json#

kind: architecture configuration

type: fully configured

name: cvw-rv64gc

description: The rv64gc configuration of Core-V Wally; RVA22S64 compliant

implemented_extensions:

- { name: I, version: "= 2.1" }

- { name: A, version: "= 2.1.0" }

- { name: M, version: "= 2.0" }

- { name: F, version: "= 2.2.0" }

- { name: D, version: "= 2.2.0" }

- { name: C, version: "= 2.0" }

- { name: B, version: "= 1.0.0" }

- { name: Zic64b, version: "= 1.0.0" }

- { name: Zicbom, version: "= 1.0.0" }

- { name: Zicbop, version: "= 1.0.0" }

- { name: Zicboz, version: "= 1.0.0" }

- { name: Ziccamoa, version: "= 1.0.0" }

- { name: Ziccif, version: "= 1.0.0" }

- { name: Zicclsm, version: "= 1.0.0" }

- { name: Ziccrse, version: "= 1.0.0" }

- { name: Zicntr, version: "= 2.0" }

- { name: Zicond, version: "= 1.0.0" }

- { name: Zicsr, version: "= 2.0" }

- { name: Zifencei, version: "= 2.0.0" }

- { name: Zihintntl, version: "= 1.0.0" }

- { name: Zihintpause, version: "= 2.0.0" }

- { name: Zihpm, version: "= 2.0.0" }

- { name: Zmmul, version: "= 1.0.0" }

- { name: Zaamo, version: "= 1.0.0" }

- { name: Zalrsc, version: "= 1.0.0" }

- { name: Za64rs, version: "= 1.0.0" }

- { name: Za128rs, version: "= 1.0.0" }

- { name: Zfa, version: "= 1.0.0" }

- { name: Zfh, version: "= 1.0.0" }

- { name: Zfhmin, version: "= 1.0.0" }

- { name: Zca, version: "= 1.0.0" }

- { name: Zcd, version: "= 1.0.0" }

- { name: Zcb, version: "= 1.0.0" }

- { name: Zba, version: "= 1.0.0" }

- { name: Zbb, version: "= 1.0.0" }

- { name: Zbs, version: "= 1.0.0" }

- { name: Zbc, version: "= 1.0.0" }

- { name: Zbkb, version: "= 1.0.0" }

- { name: Zbkc, version: "= 1.0.0" }

- { name: Zbkx, version: "= 1.0.0" }

- { name: Zknh, version: "= 1.0.0" }

- { name: Zknd, version: "= 1.0.0" }

- { name: Zkne, version: "= 1.0.0" }

- { name: Zkt, version: "= 1.0.0" }

- { name: U, version: "= 1.0.0" }

- { name: S, version: "= 1.12.0" }

- { name: Ssccptr, version: "= 1.0.0" }

- { name: Sscounterenw, version: "= 1.0.0" }

- { name: Ssstrict, version: "= 1.0.0" }

- { name: Sstc, version: "= 1.0.0" }

- { name: Sstvala, version: "= 1.0.0" }

- { name: Sstvecd, version: "= 1.0.0" }

- { name: Ssu64xl, version: "= 1.0.0" }

- { name: Sv39, version: "= 1.0.0" }

- { name: Sv48, version: "= 1.0.0" }

- { name: Sv57, version: "= 1.0.0" }

- { name: Svade, version: "= 1.0.0" }

- { name: Svadu, version: "= 1.0.0" }

- { name: Svbare, version: "= 1.0.0" }

- { name: Svinval, version: "= 1.0.0" }

- { name: Svnapot, version: "= 1.0.0" }

- { name: Svpbmt, version: "= 1.0.0" }

- { name: Svvptc, version: "= 1.0.0" }

- { name: Sm, version: "= 1.12.0" }

params:

NON_STANDARD_EXTENSION_IMPLEMENTED: false

# A params

MISALIGNED_AMO: false

LRSC_RESERVATION_STRATEGY: "reserve exactly enough to cover the access" # XLEN size reservation

LRSC_FAIL_ON_VA_SYNONYM: false

LRSC_MISALIGNED_BEHAVIOR: "always raise access fault"

LRSC_FAIL_ON_NON_EXACT_LRSC: false

MUTABLE_MISA_A: false

# M params

MUTABLE_MISA_M: false

# F params

MUTABLE_MISA_F: false

HW_MSTATUS_FS_DIRTY_UPDATE: precise

MSTATUS_FS_LEGAL_VALUES: [0, 1, 2, 3]

# D params

MUTABLE_MISA_D: false

# C params

MUTABLE_MISA_C: false

# B params

MUTABLE_MISA_B: false

# CBO params

CACHE_BLOCK_SIZE: 64

FORCE_UPGRADE_CBO_INVAL_TO_FLUSH: false

# Zicntr params

TIME_CSR_IMPLEMENTED: true

# U params

WFI_U_MODE: false

MUTABLE_MISA_U: false

U_MODE_ENDIANNESS: dynamic

UXLEN: [64]

TRAP_ON_ECALL_FROM_U: true

# S params

SEI_INTR_IMPL: true

SSI_INTR_IMPL: true

STI_INTR_IMPL: true

MUTABLE_MISA_S: false

ASID_WIDTH: 16

S_MODE_ENDIANNESS: dynamic

SXLEN: [64]

REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT: true

REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT: true

REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT: true

REPORT_VA_IN_STVAL_ON_BREAKPOINT: true

REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED: true

REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED: true

REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED: true

REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT: true

REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT: true

REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT: true

REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT: true

REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT: true

REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT: true

REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION: true

STVAL_WIDTH: 64

SCOUNTENABLE_EN:

[

true,

]

STVEC_MODES: [0, 1]

STVEC_BASE_ALIGNMENT_VECTORED: 64

SATP_MODE_BARE: true

TRAP_ON_ECALL_FROM_S: true

MSTATUS_VS_LEGAL_VALUES: [0]

# Sm params

MEI_INTR_IMPL: true

MSI_INTR_IMPL: true

MTI_INTR_IMPL: true

WFI_FINITE: false

MXLEN: 64

PRECISE_SYNCHRONOUS_EXCEPTIONS: true

TRAP_ON_ECALL_FROM_M: true

TRAP_ON_EBREAK: true

MARCHID_IMPLEMENTED: true

ARCH_ID_VALUE: 0x24

MIMPID_IMPLEMENTED: true

IMP_ID_VALUE: 0x100

VENDOR_ID_BANK: 0xC

VENDOR_ID_OFFSET: 0x2

MISALIGNED_LDST: true

MISALIGNED_LDST_EXCEPTION_PRIORITY: low

MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE: 4096 # check

MISALIGNED_SPLIT_STRATEGY: custom # We fetch the lower and upper parts with two XLEN-sized fetches and merge them

TRAP_ON_ILLEGAL_WLRL: false

TRAP_ON_UNIMPLEMENTED_INSTRUCTION: true

TRAP_ON_RESERVED_INSTRUCTION: true

TRAP_ON_UNIMPLEMENTED_CSR: true

REPORT_VA_IN_MTVAL_ON_BREAKPOINT: true

REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED: true

REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED: true

REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED: true

REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT: true

REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT: true

REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT: true

REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION: true

MTVAL_WIDTH: 64

CONFIG_PTR_ADDRESS: 0

PMA_GRANULARITY: 3 # Not explicit in config

PHYS_ADDR_WIDTH: 56

M_MODE_ENDIANNESS: dynamic

MISA_CSR_IMPLEMENTED: true

MTVEC_ACCESS: rw

MTVEC_MODES: [0, 1]

MTVEC_BASE_ALIGNMENT_DIRECT: 4

MTVEC_BASE_ALIGNMENT_VECTORED: 64

MTVEC_ILLEGAL_WRITE_BEHAVIOR: custom

NUM_PMP_ENTRIES: 16

PMP_GRANULARITY: 6

NUM_USABLE_PMP_ENTRIES: 16

PMP_NA4_SUPPORTED: false

PMP_NAPOT_SUPPORTED: true

PMP_TOR_SUPPORTED: true

HPM_COUNTER_EN:

[

false,

true,

]

HPM_COUNTER3_WIDTH: 64

HPM_COUNTER4_WIDTH: 64

HPM_COUNTER5_WIDTH: 64

HPM_COUNTER6_WIDTH: 64

HPM_COUNTER7_WIDTH: 64

HPM_COUNTER8_WIDTH: 64

HPM_COUNTER9_WIDTH: 64

HPM_COUNTER10_WIDTH: 64

HPM_COUNTER11_WIDTH: 64

HPM_COUNTER12_WIDTH: 64

HPM_COUNTER13_WIDTH: 64

HPM_COUNTER14_WIDTH: 64

HPM_COUNTER15_WIDTH: 64

HPM_COUNTER16_WIDTH: 64

HPM_COUNTER17_WIDTH: 64

HPM_COUNTER18_WIDTH: 64

HPM_COUNTER19_WIDTH: 64

HPM_COUNTER20_WIDTH: 64

HPM_COUNTER21_WIDTH: 64

HPM_COUNTER22_WIDTH: 64

HPM_COUNTER23_WIDTH: 64

HPM_COUNTER24_WIDTH: 64

HPM_COUNTER25_WIDTH: 64

HPM_COUNTER26_WIDTH: 64

HPM_COUNTER27_WIDTH: 64

HPM_COUNTER28_WIDTH: 64

HPM_COUNTER29_WIDTH: 64

HPM_COUNTER30_WIDTH: 64

HPM_COUNTER31_WIDTH: 64

HPM_EVENTS: [0]

MCOUNTINHIBIT_IMPLEMENTED: true

COUNTINHIBIT_EN:

[

true,

false,

true,

]

MCOUNTENABLE_EN:

[

true,

]

# instruction-address-misaligned cannot occur with Zca, so medeleg[0] is read-only zero (csrm.sv MEDELEG_MASK)

MEDELEG_DELEGATABLE:

[

false,

true,

false,

true,

false,

true,

false,

]

MIDELEG_DELEGATABLE:

[

false,

true,

false,

true,

false,

true,

false,

]

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