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    162 repositories

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •61•246•21•14•Updated Oct 6, 2026Oct 6, 2026

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilog
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •141•284•3•8•Updated Oct 6, 2026Oct 6, 2026

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      pythongeneratorsystemverilog
      pythongeneratorsystemverilognocaxi
      SystemVerilog
      •
      Apache License 2.0
      •80•356•23•8•Updated Oct 7, 2026Oct 7, 2026

    • redundancy_cells

      Public
      SystemVerilog IPs and Modules for architectural redundancy designs.
      SystemVerilog
      •
      Other
      •12•23•0•7•Updated Oct 6, 2026Oct 6, 2026

    • softex

      Public
      SystemVerilog
      •
      Other
      •5•18•1•0•Updated Oct 5, 2026Oct 5, 2026

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •35•119•5•2•Updated Oct 5, 2026Oct 5, 2026

    • cv-hpdcache

      Public
      RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
      SystemVerilog
      •
      Other
      •57•0•0•1•Updated Oct 1, 2026Oct 1, 2026

    • serial_link

      Public
      A simple, scalable, source-synchronous, all-digital DDR link
      SystemVerilog
      •
      Other
      •15•42•0•1•Updated Oct 1, 2026Oct 1, 2026

    • neureka

      Public
      2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
      SystemVerilog
      •
      Other
      •9•42•4•11•Updated Sep 30, 2026Sep 30, 2026

    • redmule

      Public
      GEMM and GEMM-Ops accelerator for PULP systems
      SystemVerilog
      •
      Other
      •28•123•3•3•Updated Sep 30, 2026Sep 30, 2026

    • memory_island

      Public
      An interleaved high-throughput low-contention L2 scratchpad memory.
      SystemVerilog
      •
      Other
      •7•6•5•4•Updated Sep 25, 2026Sep 25, 2026

    • eda-benchmarks

      Public
      SystemVerilog
      •
      Other
      •0•5•1•0•Updated Sep 24, 2026Sep 24, 2026

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardware
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •374•1.7k•45•17•Updated Sep 24, 2026Sep 24, 2026

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •206•807•7•2•Updated Sep 18, 2026Sep 18, 2026

    • ace

      Public
      SystemVerilog
      •
      Other
      •7•27•0•1•Updated Oct 1, 2026Oct 1, 2026

    • riscv-dbg

      Public
      RISC-V Debug Support for our PULP RISC-V Cores
      riscvdebug
      riscvdebug
      SystemVerilog
      •
      Other
      •102•328•17•3•Updated Sep 15, 2026Sep 15, 2026

    • cvfpu

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      •
      Apache License 2.0
      •173•23•0•7•Updated Sep 30, 2026Sep 30, 2026

    • axi_llc

      Public
      SystemVerilog
      •
      Other
      •28•37•5•4•Updated Sep 10, 2026Sep 10, 2026

    • obi

      Public
      OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
      SystemVerilog
      •
      Other
      •16•25•3•10•Updated Sep 10, 2026Sep 10, 2026

    • hyperbus

      Public
      SystemVerilog
      •
      Other
      •11•40•2•7•Updated Sep 30, 2026Sep 30, 2026

    • cluster_interconnect

      Public
      SystemVerilog
      •
      Other
      •17•18•1•3•Updated Sep 5, 2026Sep 5, 2026

    • pulp-c910

      Public
      PULP C910, a superscalar out-of-order RISC-V core adapted from T-Head's openC910 (Alibaba Group) and integrated into the PULP ecosystem with several modificatio…
      SystemVerilog
      •
      Other
      •9•20•0•0•Updated Aug 25, 2026Aug 25, 2026

    • obi_peripherals

      Public
      Collection of peripheral IPs using the Open Bus Interface (OBI)
      SystemVerilog
      •
      Other
      •2•6•1•1•Updated Aug 24, 2026Aug 24, 2026

    • croc-ips

      Public
      Reusable IPs targetting student tapeouts based on the Croc SoC.
      SystemVerilog
      •
      Other
      •0•1•0•1•Updated Aug 24, 2026Aug 24, 2026

    • tech_cells_generic

      Public
      Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
      SystemVerilog
      •
      Other
      •46•102•2•4•Updated Aug 20, 2026Aug 20, 2026

    • axi_stream

      Public
      SystemVerilog
      •
      Other
      •8•9•0•2•Updated Aug 12, 2026Aug 12, 2026

    • clint

      Public
      RISC-V Core Local Interrupt Controller (CLINT)
      SystemVerilog
      •
      Other
      •7•34•0•0•Updated Aug 7, 2026Aug 7, 2026

    • register_interface

      Public
      Generic Register Interface (contains various adapters)
      SystemVerilog
      •
      Other
      •41•140•4•9•Updated Aug 6, 2026Aug 6, 2026

    • dram_rtl_sim

      Public
      SystemVerilog
      •
      Other
      •11•22•1•2•Updated Aug 6, 2026Aug 6, 2026

    • apb

      Public
      APB Logic
      SystemVerilog
      •
      Other
      •24•29•2•5•Updated Sep 24, 2026Sep 24, 2026
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