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Taojunshenpmsjtmichaelwoeristerlearn-build-service-prod[bot]Pedro Justo
authored
5/29/2023 AM Publish (MicrosoftDocs#4928)
* Volatile vs Non-volatile is a very Microsoft specific terminology. Out in the industry, register calling convention assignment are more frequently referred to as Caller vs Callee saved. Also, x18 is a reserved register, so it is neither Caller nor Callee Saved. * Add links to C28306 and C28307. * Incorporate feedback: Restrict changes to the registers that previously had objectively incorrect descriptions. * Push missing merge. * Push missing merge. * Fix description of paramter/result registers. x1, x8 and v1-v3 can also be result registers. --------- Co-authored-by: Pedro Miguel Justo <40605312+pmsjt@users.noreply.github.com> Co-authored-by: Michael Woerister <michaelwoerister@posteo> Co-authored-by: learn-build-service-prod[bot] <113403604+learn-build-service-prod[bot]@users.noreply.github.com> Co-authored-by: Pedro Justo <pmsjt@Blackbird.home> Co-authored-by: Courtney Wales <62625502+Court72@users.noreply.github.com> Co-authored-by: huypub <38988242+huypub@users.noreply.github.com> Co-authored-by: prmerger-automator[bot] <40007230+prmerger-automator[bot]@users.noreply.github.com>
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‎docs/build/arm64-windows-abi-conventions.md‎

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The AArch64 architecture supports 32 integer registers:
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| Register | Volatile? | Role |
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| Register | Volatility | Role |
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| - | - | - |
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| x0 | Volatile | Parameter/scratch register 1, result register |
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| x1-x7 | Volatile | Parameter/scratch register 2-8 |
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| x8-x15 | Volatile | Scratch registers |
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| x0-x8 | Volatile | Parameter/Result scratch registers |
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| x9-x15 | Volatile | Scratch registers |
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| x16-x17 | Volatile | Intra-procedure-call scratch registers |
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| x18 | Non-volatile | Platform register: in kernel mode, points to KPCR for the current processor; in user mode, points to TEB |
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| x18 | N/A | Reserved platform register: in kernel mode, points to KPCR for the current processor; In user mode, points to TEB |
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| x19-x28 | Non-volatile | Scratch registers |
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| x29/fp | Non-volatile | Frame pointer |
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| x30/lr | Non-volatile | Link registers |
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| x30/lr | Both | Link Register: Callee function must preserve it for its own return, but caller's value will be lost. |
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Each register may be accessed as a full 64-bit value (via x0-x30) or as a 32-bit value (via w0-w30). 32-bit operations zero-extend their results up to 64 bits.
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The AArch64 architecture also supports 32 floating-point/SIMD registers, summarized below:
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| Register | Volatile? | Role |
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| Register | Volatility | Role |
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| - | - | - |
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| v0 | Volatile | Parameter/scratch register 1, result register |
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| v1-v7 | Volatile | Parameter/scratch registers 2-8 |
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| v8-v15 | Non-volatile | Scratch registers (only the low 64 bits are non-volatile) |
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| v0-v7 | Volatile | Parameter/Result scratch registers |
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| v8-v15 | Both | Low 64 bits are Non-Volatile. High 64 bits are Volatile. |
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| v16-v31 | Volatile | Scratch registers |
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Each register may be accessed as a full 128-bit value (via v0-v31 or q0-q31). It may be accessed as a 64-bit value (via d0-d31), as a 32-bit value (via s0-s31), as a 16-bit value (via h0-h31), or as an 8-bit value (via b0-b31). Accesses smaller than 128 bits only access the lower bits of the full 128-bit register. They leave the remaining bits untouched unless otherwise specified. (AArch64 is different from AArch32, where the smaller registers were packed on top of the larger registers.)
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The floating-point control register (FPCR) has certain requirements on the various bitfields within it:
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| Bits | Meaning | Volatile? | Role |
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| Bits | Meaning | Volatility | Role |
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| - | - | - | - |
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| 26 | AHP | Non-Volatile | Alternative half-precision control. |
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| 25 | DN | Non-Volatile | Default NaN mode control. |

‎docs/code-quality/c28306.md‎

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> The annotation on parameter is obsolescent
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Use `_String_length_` with the appropriate SAL2 annotation instead.
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## See also
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[Intrinsic Functions](./intrinsic-functions.md)

‎docs/code-quality/c28307.md‎

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> The annotation on parameter is obsolescent
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Use `_String_length_` with the appropriate SAL2 annotation instead.
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## See also
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[Intrinsic Functions](./intrinsic-functions.md)

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