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Matthew Wahab
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[AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP instruction.
ARMv8.2 adds the new system instruction DC CVAP. This patch series adds support for this instruction to binutils, enabled when -march=armv8.2-a is selected. The AArch64 binutils record of some system registers uses a boolean value to hold the single flag currently supported for them. To allow these registers to be limited to specific architectures, the first patch in this series replaces the boolean flag with a bitset and feature test. include/opcode/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags. (aarch64_sys_ins_reg_has_xt): Declare. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt with aarch64_sys_ins_reg_has_xt. (aarch64_ext_sysins_op): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): Likewise. (F_HASXT): New. (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg. (aarch64_sys_regs_dc): Likewise. (aarch64_sys_regs_at): Likewise. (aarch64_sys_regs_tlbi): Likewise. (aarch64_sys_ins_reg_has_xt): New. Change-Id: I363637a6c3f54d7ffff953b3a0734e8139cae819
1 parent 762f774 commit ea2deee

5 files changed

Lines changed: 82 additions & 48 deletions

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‎include/opcode/ChangeLog‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,8 @@
1+
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
2+
3+
* aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
4+
(aarch64_sys_ins_reg_has_xt): Declare.
5+
16
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
27

38
* aarch64.h (AARCH64_FEATURE_RAS): New.

‎include/opcode/aarch64.h‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -672,9 +672,11 @@ typedef struct
672672
{
673673
const char *name;
674674
uint32_t value;
675-
int has_xt;
675+
uint32_t flags ;
676676
} aarch64_sys_ins_reg;
677677

678+
extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
679+
678680
extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
679681
extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
680682
extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];

‎opcodes/ChangeLog‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,16 @@
1+
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
2+
3+
* aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
4+
with aarch64_sys_ins_reg_has_xt.
5+
(aarch64_ext_sysins_op): Likewise.
6+
* aarch64-opc.c (operand_general_constraint_met_p): Likewise.
7+
(F_HASXT): New.
8+
(aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
9+
(aarch64_sys_regs_dc): Likewise.
10+
(aarch64_sys_regs_at): Likewise.
11+
(aarch64_sys_regs_tlbi): Likewise.
12+
(aarch64_sys_ins_reg_has_xt): New.
13+
114
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
215

316
* aarch64-opc.c (aarch64_sys_regs): Add "uao".

‎opcodes/aarch64-dis.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -248,7 +248,7 @@ aarch64_ext_regrt_sysins (const aarch64_operand *self, aarch64_opnd_info *info,
248248
/* This will make the constraint checking happy and more importantly will
249249
help the disassembler determine whether this operand is optional or
250250
not. */
251-
info->present = inst->operands[0].sysins_op->has_xt;
251+
info->present = aarch64_sys_ins_reg_has_xt (inst->operands[0].sysins_op);
252252

253253
return 1;
254254
}
@@ -1034,7 +1034,7 @@ aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
10341034
DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.",
10351035
info->sysins_op->name,
10361036
(unsigned)info->sysins_op->value,
1037-
info->sysins_op->has_xt, i);
1037+
aarch64_sys_ins_reg_has_xt (info->sysins_op), i);
10381038
return 1;
10391039
}
10401040

‎opcodes/aarch64-opc.c‎

Lines changed: 59 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -1279,12 +1279,14 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
12791279
{
12801280
assert (idx == 1 && (aarch64_get_operand_class (opnds[0].type)
12811281
== AARCH64_OPND_CLASS_SYSTEM));
1282-
if (opnds[1].present && !opnds[0].sysins_op->has_xt)
1282+
if (opnds[1].present
1283+
&& !aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
12831284
{
12841285
set_other_error (mismatch_detail, idx, _("extraneous register"));
12851286
return 0;
12861287
}
1287-
if (!opnds[1].present && opnds[0].sysins_op->has_xt)
1288+
if (!opnds[1].present
1289+
&& aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
12881290
{
12891291
set_other_error (mismatch_detail, idx, _("missing register"));
12901292
return 0;
@@ -2756,6 +2758,12 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
27562758
#endif
27572759
#define F_ARCHEXT 0x2 /* Architecture dependent system register. */
27582760

2761+
#ifdef F_HASXT
2762+
#undef F_HASXT
2763+
#endif
2764+
#define F_HASXT 0x4 /* System instruction register <Xt>
2765+
operand. */
2766+
27592767

27602768
/* TODO there are two more issues need to be resolved
27612769
1. handle read-only and write-only system registers
@@ -3244,77 +3252,83 @@ const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
32443252
{
32453253
{ "ialluis", CPENS(0,C7,C1,0), 0 },
32463254
{ "iallu", CPENS(0,C7,C5,0), 0 },
3247-
{ "ivau", CPENS(3,C7,C5,1), 1 },
3255+
{ "ivau", CPENS (3, C7, C5, 1), F_HASXT },
32483256
{ 0, CPENS(0,0,0,0), 0 }
32493257
};
32503258

32513259
const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
32523260
{
3253-
{ "zva", CPENS(3,C7,C4,1), 1 },
3254-
{ "ivac", CPENS(0,C7,C6,1), 1 },
3255-
{ "isw", CPENS(0,C7,C6,2), 1 },
3256-
{ "cvac", CPENS(3,C7,C10,1), 1 },
3257-
{ "csw", CPENS(0,C7,C10,2), 1 },
3258-
{ "cvau", CPENS(3,C7,C11,1), 1 },
3259-
{ "civac", CPENS(3,C7,C14,1), 1 },
3260-
{ "cisw", CPENS(0,C7,C14,2), 1 },
3261+
{ "zva", CPENS (3, C7, C4, 1), F_HASXT },
3262+
{ "ivac", CPENS (0, C7, C6, 1), F_HASXT },
3263+
{ "isw", CPENS (0, C7, C6, 2), F_HASXT },
3264+
{ "cvac", CPENS (3, C7, C10, 1), F_HASXT },
3265+
{ "csw", CPENS (0, C7, C10, 2), F_HASXT },
3266+
{ "cvau", CPENS (3, C7, C11, 1), F_HASXT },
3267+
{ "civac", CPENS (3, C7, C14, 1), F_HASXT },
3268+
{ "cisw", CPENS (0, C7, C14, 2), F_HASXT },
32613269
{ 0, CPENS(0,0,0,0), 0 }
32623270
};
32633271

32643272
const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
32653273
{
3266-
{ "s1e1r", CPENS(0,C7,C8,0), 1 },
3267-
{ "s1e1w", CPENS(0,C7,C8,1), 1 },
3268-
{ "s1e0r", CPENS(0,C7,C8,2), 1 },
3269-
{ "s1e0w", CPENS(0,C7,C8,3), 1 },
3270-
{ "s12e1r", CPENS(4,C7,C8,4), 1 },
3271-
{ "s12e1w", CPENS(4,C7,C8,5), 1 },
3272-
{ "s12e0r", CPENS(4,C7,C8,6), 1 },
3273-
{ "s12e0w", CPENS(4,C7,C8,7), 1 },
3274-
{ "s1e2r", CPENS(4,C7,C8,0), 1 },
3275-
{ "s1e2w", CPENS(4,C7,C8,1), 1 },
3276-
{ "s1e3r", CPENS(6,C7,C8,0), 1 },
3277-
{ "s1e3w", CPENS(6,C7,C8,1), 1 },
3274+
{ "s1e1r", CPENS (0, C7, C8, 0), F_HASXT },
3275+
{ "s1e1w", CPENS (0, C7, C8, 1), F_HASXT },
3276+
{ "s1e0r", CPENS (0, C7, C8, 2), F_HASXT },
3277+
{ "s1e0w", CPENS (0, C7, C8, 3), F_HASXT },
3278+
{ "s12e1r", CPENS (4, C7, C8, 4), F_HASXT },
3279+
{ "s12e1w", CPENS (4, C7, C8, 5), F_HASXT },
3280+
{ "s12e0r", CPENS (4, C7, C8, 6), F_HASXT },
3281+
{ "s12e0w", CPENS (4, C7, C8, 7), F_HASXT },
3282+
{ "s1e2r", CPENS (4, C7, C8, 0), F_HASXT },
3283+
{ "s1e2w", CPENS (4, C7, C8, 1), F_HASXT },
3284+
{ "s1e3r", CPENS (6, C7, C8, 0), F_HASXT },
3285+
{ "s1e3w", CPENS (6, C7, C8, 1), F_HASXT },
32783286
{ 0, CPENS(0,0,0,0), 0 }
32793287
};
32803288

32813289
const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
32823290
{
32833291
{ "vmalle1", CPENS(0,C8,C7,0), 0 },
3284-
{ "vae1", CPENS(0,C8,C7,1), 1 },
3285-
{ "aside1", CPENS(0,C8,C7,2), 1 },
3286-
{ "vaae1", CPENS(0,C8,C7,3), 1 },
3292+
{ "vae1", CPENS (0, C8, C7, 1), F_HASXT },
3293+
{ "aside1", CPENS (0, C8, C7, 2), F_HASXT },
3294+
{ "vaae1", CPENS (0, C8, C7, 3), F_HASXT },
32873295
{ "vmalle1is", CPENS(0,C8,C3,0), 0 },
3288-
{ "vae1is", CPENS(0,C8,C3,1), 1 },
3289-
{ "aside1is", CPENS(0,C8,C3,2), 1 },
3290-
{ "vaae1is", CPENS(0,C8,C3,3), 1 },
3291-
{ "ipas2e1is", CPENS(4,C8,C0,1), 1 },
3292-
{ "ipas2le1is",CPENS(4,C8,C0,5), 1 },
3293-
{ "ipas2e1", CPENS(4,C8,C4,1), 1 },
3294-
{ "ipas2le1", CPENS(4,C8,C4,5), 1 },
3295-
{ "vae2", CPENS(4,C8,C7,1), 1 },
3296-
{ "vae2is", CPENS(4,C8,C3,1), 1 },
3296+
{ "vae1is", CPENS (0, C8, C3, 1), F_HASXT },
3297+
{ "aside1is", CPENS (0, C8, C3, 2), F_HASXT },
3298+
{ "vaae1is", CPENS (0, C8, C3, 3), F_HASXT },
3299+
{ "ipas2e1is", CPENS (4, C8, C0, 1), F_HASXT },
3300+
{ "ipas2le1is",CPENS (4, C8, C0, 5), F_HASXT },
3301+
{ "ipas2e1", CPENS (4, C8, C4, 1), F_HASXT },
3302+
{ "ipas2le1", CPENS (4, C8, C4, 5), F_HASXT },
3303+
{ "vae2", CPENS (4, C8, C7, 1), F_HASXT },
3304+
{ "vae2is", CPENS (4, C8, C3, 1), F_HASXT },
32973305
{ "vmalls12e1",CPENS(4,C8,C7,6), 0 },
32983306
{ "vmalls12e1is",CPENS(4,C8,C3,6), 0 },
3299-
{ "vae3", CPENS(6,C8,C7,1), 1 },
3300-
{ "vae3is", CPENS(6,C8,C3,1), 1 },
3307+
{ "vae3", CPENS (6, C8, C7, 1), F_HASXT },
3308+
{ "vae3is", CPENS (6, C8, C3, 1), F_HASXT },
33013309
{ "alle2", CPENS(4,C8,C7,0), 0 },
33023310
{ "alle2is", CPENS(4,C8,C3,0), 0 },
33033311
{ "alle1", CPENS(4,C8,C7,4), 0 },
33043312
{ "alle1is", CPENS(4,C8,C3,4), 0 },
33053313
{ "alle3", CPENS(6,C8,C7,0), 0 },
33063314
{ "alle3is", CPENS(6,C8,C3,0), 0 },
3307-
{ "vale1is", CPENS(0,C8,C3,5), 1 },
3308-
{ "vale2is", CPENS(4,C8,C3,5), 1 },
3309-
{ "vale3is", CPENS(6,C8,C3,5), 1 },
3310-
{ "vaale1is", CPENS(0,C8,C3,7), 1 },
3311-
{ "vale1", CPENS(0,C8,C7,5), 1 },
3312-
{ "vale2", CPENS(4,C8,C7,5), 1 },
3313-
{ "vale3", CPENS(6,C8,C7,5), 1 },
3314-
{ "vaale1", CPENS(0,C8,C7,7), 1 },
3315+
{ "vale1is", CPENS (0, C8, C3, 5), F_HASXT },
3316+
{ "vale2is", CPENS (4, C8, C3, 5), F_HASXT },
3317+
{ "vale3is", CPENS (6, C8, C3, 5), F_HASXT },
3318+
{ "vaale1is", CPENS (0, C8, C3, 7), F_HASXT },
3319+
{ "vale1", CPENS (0, C8, C7, 5), F_HASXT },
3320+
{ "vale2", CPENS (4, C8, C7, 5), F_HASXT },
3321+
{ "vale3", CPENS (6, C8, C7, 5), F_HASXT },
3322+
{ "vaale1", CPENS (0, C8, C7, 7), F_HASXT },
33153323
{ 0, CPENS(0,0,0,0), 0 }
33163324
};
33173325

3326+
bfd_boolean
3327+
aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
3328+
{
3329+
return (sys_ins_reg->flags & F_HASXT) != 0;
3330+
}
3331+
33183332
#undef C0
33193333
#undef C1
33203334
#undef C2

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