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Yao Qi
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Return -1 on memory error in print_insn_msp430
Disassemblers in opcodes return -1 on memory error, but msp430 doesn't follow this convention. If I change GDB not to throw exception in disassemble_info.memory_error_func and rely on the return value of disassembler, I'll get the following output. (gdb) disassemble 0x0,+8 Dump of assembler code from 0x0 to 0x8: 0x00000000: .word 0xffff; ???? 0x00000002: .word 0xffff; ???? 0x00000004: .word 0xffff; ???? 0x00000006: .word 0xffff; ???? End of assembler dump. This patch teaches print_insn_msp430 and its callees to return -1 on memory error. opcodes: 2017-01-12 Yao Qi <yao.qi@linaro.org> * msp430-dis.c (msp430_singleoperand): Return -1 if msp430dis_opcode_signed returns false. (msp430_doubleoperand): Likewise. (msp430_branchinstr): Return -1 if msp430dis_opcode_unsigned returns false. (msp430x_calla_instr): Likewise. (print_insn_msp430): Likewise.
1 parent eed0b5b commit d95014a

2 files changed

Lines changed: 99 additions & 14 deletions

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‎opcodes/ChangeLog‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,13 @@
1+
2017-01-12 Yao Qi <yao.qi@linaro.org>
2+
3+
* msp430-dis.c (msp430_singleoperand): Return -1 if
4+
msp430dis_opcode_signed returns false.
5+
(msp430_doubleoperand): Likewise.
6+
(msp430_branchinstr): Return -1 if
7+
msp430dis_opcode_unsigned returns false.
8+
(msp430x_calla_instr): Likewise.
9+
(print_insn_msp430): Likewise.
10+
111
2017-01-05 Nick Clifton <nickc@redhat.com>
212

313
PR 20946

‎opcodes/msp430-dis.c‎

Lines changed: 89 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -270,6 +270,8 @@ msp430_singleoperand (disassemble_info *info,
270270
(long)((addr + 2 + dst) & 0xfffff));
271271
}
272272
}
273+
else
274+
return -1;
273275
}
274276
else if (regd == 2)
275277
{
@@ -285,6 +287,8 @@ msp430_singleoperand (disassemble_info *info,
285287
sprintf (op, "&0x%05x", dst & 0xfffff);
286288
}
287289
}
290+
else
291+
return -1;
288292
}
289293
else
290294
{
@@ -300,6 +304,8 @@ msp430_singleoperand (disassemble_info *info,
300304
}
301305
sprintf (op, "%d(r%d)", dst, regd);
302306
}
307+
else
308+
return -1;
303309
}
304310
}
305311
break;
@@ -346,6 +352,8 @@ msp430_singleoperand (disassemble_info *info,
346352
sprintf (comm, "#0x%05x", dst);
347353
}
348354
}
355+
else
356+
return -1;
349357
}
350358
else
351359
* cycles = print_as3_reg_name (regd, op, comm, 1, 1, 3);
@@ -370,6 +378,8 @@ msp430_singleoperand (disassemble_info *info,
370378
(long)((addr + 2 + dst) & 0xfffff));
371379
}
372380
}
381+
else
382+
return -1;
373383
}
374384
else if (regd == 2)
375385
{
@@ -384,6 +394,8 @@ msp430_singleoperand (disassemble_info *info,
384394
sprintf (op, "&0x%05x", dst & 0xfffff);
385395
}
386396
}
397+
else
398+
return -1;
387399
}
388400
else if (regd == 3)
389401
{
@@ -407,6 +419,8 @@ msp430_singleoperand (disassemble_info *info,
407419
if (dst > 9 || dst < 0)
408420
sprintf (comm, "%05x", dst);
409421
}
422+
else
423+
return -1;
410424
}
411425
}
412426
break;
@@ -511,6 +525,8 @@ msp430_doubleoperand (disassemble_info *info,
511525
(long)((addr + 2 + dst) & 0xfffff));
512526
}
513527
}
528+
else
529+
return -1;
514530
}
515531
else if (regd == 2)
516532
{
@@ -526,6 +542,8 @@ msp430_doubleoperand (disassemble_info *info,
526542
if (src != dst)
527543
return 0;
528544
}
545+
else
546+
return -1;
529547
cmd_len += 4;
530548
*cycles = 6;
531549
sprintf (op1, "&0x%04x", PS (dst));
@@ -535,6 +553,8 @@ msp430_doubleoperand (disassemble_info *info,
535553
sprintf (op1, "&0x%05x", dst & 0xfffff);
536554
}
537555
}
556+
else
557+
return -1;
538558
}
539559
else
540560
{
@@ -553,6 +573,8 @@ msp430_doubleoperand (disassemble_info *info,
553573
if (dst > 9 || dst < -9)
554574
sprintf (comm1, "#0x%05x", dst);
555575
}
576+
else
577+
return -1;
556578
}
557579
}
558580

@@ -613,6 +635,8 @@ msp430_doubleoperand (disassemble_info *info,
613635
sprintf (comm1, "0x%05x", dst & 0xfffff);
614636
}
615637
}
638+
else
639+
return -1;
616640
}
617641
else
618642
* cycles = print_as3_reg_name (regs, op1, comm1, 1, 1, 2);
@@ -640,6 +664,8 @@ msp430_doubleoperand (disassemble_info *info,
640664
(long) ((addr + 2 + dst) & 0xfffff));
641665
}
642666
}
667+
else
668+
return -1;
643669
}
644670
else if (regs == 2)
645671
{
@@ -658,6 +684,8 @@ msp430_doubleoperand (disassemble_info *info,
658684
* comm1 = 0;
659685
}
660686
}
687+
else
688+
return -1;
661689
}
662690
else if (regs == 3)
663691
{
@@ -683,6 +711,8 @@ msp430_doubleoperand (disassemble_info *info,
683711
if (dst > 9 || dst < -9)
684712
sprintf (comm1, "0x%05x", dst);
685713
}
714+
else
715+
return -1;
686716
}
687717
}
688718

@@ -728,6 +758,8 @@ msp430_doubleoperand (disassemble_info *info,
728758
(long)((addr + cmd_len + dst) & 0xfffff));
729759
}
730760
}
761+
else
762+
return -1;
731763
cmd_len += 2;
732764
}
733765
else if (regd == 2)
@@ -743,6 +775,8 @@ msp430_doubleoperand (disassemble_info *info,
743775
sprintf (op2, "&0x%05x", dst & 0xfffff);
744776
}
745777
}
778+
else
779+
return -1;
746780
}
747781
else
748782
{
@@ -761,6 +795,8 @@ msp430_doubleoperand (disassemble_info *info,
761795
}
762796
sprintf (op2, "%d(r%d)", dst, regd);
763797
}
798+
else
799+
return -1;
764800
}
765801
}
766802

@@ -821,6 +857,8 @@ msp430_branchinstr (disassemble_info *info,
821857
cmd_len += 2;
822858
sprintf (op1, "#0x%04x", PS (udst));
823859
}
860+
else
861+
return -1;
824862
}
825863
else
826864
* cycles = print_as3_reg_name (regs, op1, comm1, 1, 1, 2);
@@ -840,6 +878,8 @@ msp430_branchinstr (disassemble_info *info,
840878
sprintf (comm1, "PC rel. 0x%04x",
841879
PS ((short) addr + 2 + dst));
842880
}
881+
else
882+
return -1;
843883
}
844884
else if (regs == 2)
845885
{
@@ -849,6 +889,8 @@ msp430_branchinstr (disassemble_info *info,
849889
cmd_len += 2;
850890
sprintf (op1, "&0x%04x", PS (udst));
851891
}
892+
else
893+
return -1;
852894
}
853895
else if (regs == 3)
854896
{
@@ -864,6 +906,8 @@ msp430_branchinstr (disassemble_info *info,
864906
cmd_len += 2;
865907
sprintf (op1, "%d(r%d)", dst, regs);
866908
}
909+
else
910+
return -1;
867911
}
868912
}
869913

@@ -903,6 +947,8 @@ msp430x_calla_instr (disassemble_info * info,
903947
else
904948
sprintf (comm1, "0x%05x", dst);
905949
}
950+
else
951+
return -1;
906952
break;
907953

908954
case 6: /* CALLA @Rdst */
@@ -923,6 +969,8 @@ msp430x_calla_instr (disassemble_info * info,
923969
sprintf (op1, "&%d", (ureg << 16) + udst);
924970
sprintf (comm1, "0x%05x", (ureg << 16) + udst);
925971
}
972+
else
973+
return -1;
926974
break;
927975

928976
case 9: /* CALLA pcrel-sym */
@@ -934,6 +982,8 @@ msp430x_calla_instr (disassemble_info * info,
934982
sprintf (comm1, "PC rel. 0x%05lx",
935983
(long) (addr + 2 + dst + (reg << 16)));
936984
}
985+
else
986+
return -1;
937987
break;
938988

939989
case 11: /* CALLA #imm20 */
@@ -944,6 +994,8 @@ msp430x_calla_instr (disassemble_info * info,
944994
sprintf (op1, "#%d", (ureg << 16) + udst);
945995
sprintf (comm1, "0x%05x", (ureg << 16) + udst);
946996
}
997+
else
998+
return -1;
947999
break;
9481000

9491001
default:
@@ -969,10 +1021,7 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
9691021
unsigned short bits;
9701022

9711023
if (! msp430dis_opcode_unsigned (addr, info, &insn, NULL))
972-
{
973-
prin (stream, ".word 0xffff; ????");
974-
return 2;
975-
}
1024+
return -1;
9761025

9771026
if (((int) addr & 0xffff) > 0xffdf)
9781027
{
@@ -989,11 +1038,7 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
9891038
extension_word = insn;
9901039
addr += 2;
9911040
if (! msp430dis_opcode_unsigned (addr, info, &insn, NULL))
992-
{
993-
prin (stream, ".word 0x%04x, 0xffff; ????",
994-
extension_word);
995-
return 4;
996-
}
1041+
return -1;
9971042
}
9981043

9991044
for (opcode = msp430_opcodes; opcode->name; opcode++)
@@ -1011,9 +1056,13 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
10111056
&& (insn & 0x000f) == 0
10121057
&& (insn & 0x0080) == 0)
10131058
{
1014-
cmd_len +=
1059+
int ret =
10151060
msp430_branchinstr (info, opcode, addr, insn, op1, comm1,
10161061
&cycles);
1062+
1063+
if (ret == -1)
1064+
return -1;
1065+
cmd_len += ret;
10171066
if (cmd_len)
10181067
break;
10191068
}
@@ -1022,10 +1071,14 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
10221071
{
10231072
int n;
10241073
int reg;
1074+
int ret;
10251075

10261076
case 4:
1027-
cmd_len += msp430x_calla_instr (info, addr, insn,
1028-
op1, comm1, & cycles);
1077+
ret = msp430x_calla_instr (info, addr, insn,
1078+
op1, comm1, & cycles);
1079+
if (ret == -1)
1080+
return -1;
1081+
cmd_len += ret;
10291082
break;
10301083

10311084
case 5: /* PUSHM/POPM */
@@ -1080,6 +1133,8 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
10801133
if (n > 9 || n < 0)
10811134
sprintf (comm1, "0x%05x", n);
10821135
}
1136+
else
1137+
return -1;
10831138
cmd_len = 4;
10841139
}
10851140
sprintf (op2, "r%d", reg);
@@ -1120,6 +1175,8 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
11201175
if (strcmp (opcode->name, "bra") != 0)
11211176
sprintf (op2, "r%d", reg);
11221177
}
1178+
else
1179+
return -1;
11231180
break;
11241181

11251182
case 3: /* MOVA x(Rsrc), Rdst */
@@ -1139,6 +1196,8 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
11391196
sprintf (comm1, "0x%05x", n);
11401197
}
11411198
}
1199+
else
1200+
return -1;
11421201
break;
11431202

11441203
case 6: /* MOVA Rsrc, &abs20 */
@@ -1152,6 +1211,8 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
11521211
if (reg > 9 || reg < 0)
11531212
sprintf (comm2, "0x%05x", reg);
11541213
}
1214+
else
1215+
return -1;
11551216
break;
11561217

11571218
case 7: /* MOVA Rsrc, x(Rdst) */
@@ -1169,6 +1230,8 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
11691230
sprintf (comm2, "0x%05x", n);
11701231
}
11711232
}
1233+
else
1234+
return -1;
11721235
break;
11731236

11741237
case 8: /* MOVA #imm20, Rdst */
@@ -1185,6 +1248,8 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
11851248
if (strcmp (opcode->name, "bra") != 0)
11861249
sprintf (op2, "r%d", reg);
11871250
}
1251+
else
1252+
return -1;
11881253
break;
11891254

11901255
case 12: /* MOVA Rsrc, Rdst */
@@ -1206,15 +1271,21 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
12061271

12071272
switch (opcode->insn_opnumb)
12081273
{
1274+
int ret;
1275+
12091276
case 0:
12101277
cmd_len += msp430_nooperands (opcode, addr, insn, comm1, &cycles);
12111278
break;
12121279
case 2:
1213-
cmd_len +=
1280+
ret =
12141281
msp430_doubleoperand (info, opcode, addr, insn, op1, op2,
12151282
comm1, comm2,
12161283
extension_word,
12171284
&cycles);
1285+
1286+
if (ret == -1)
1287+
return -1;
1288+
cmd_len += ret;
12181289
if (insn & BYTE_OPERATION)
12191290
{
12201291
if (extension_word != 0 && ((extension_word & BYTE_OPERATION) == 0))
@@ -1235,10 +1306,14 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
12351306

12361307
break;
12371308
case 1:
1238-
cmd_len +=
1309+
ret =
12391310
msp430_singleoperand (info, opcode, addr, insn, op1, comm1,
12401311
extension_word,
12411312
&cycles);
1313+
1314+
if (ret == -1)
1315+
return -1;
1316+
cmd_len += ret;
12421317
if (extension_word
12431318
&& (strcmp (opcode->name, "swpb") == 0
12441319
|| strcmp (opcode->name, "sxt") == 0))

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