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Claudiu Zissulescu
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[ARC] Add checking for LP_COUNT reg usage, improve error reporting.
gas/ 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (find_opcode_match): New function argument errmsg. (assemble_tokens): Collect and report the eventual error message found during opcode matching process. * testsuite/gas/arc/lpcount-err.s: New file. * testsuite/gas/arc/add_s-err.s: Update error message. opcode/ 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (insert_ra_chk): New function. (insert_rb_chk): Likewise. (insert_rad): Update text error message. (insert_rcd): Likewise. (insert_rhv2): Likewise. (insert_r0): Likewise. (insert_r1): Likewise. (insert_r2): Likewise. (insert_r3): Likewise. (insert_sp): Likewise. (insert_gp): Likewise. (insert_pcl): Likewise. (insert_blink): Likewise. (insert_ilink1): Likewise. (insert_ilink2): Likewise. (insert_ras): Likewise. (insert_rbs): Likewise. (insert_rcs): Likewise. (insert_simm3s): Likewise. (insert_rrange): Likewise. (insert_fpel): Likewise. (insert_blinkel): Likewise. (insert_pcel): Likewise. (insert_nps_3bit_dst): Likewise. (insert_nps_3bit_dst_short): Likewise. (insert_nps_3bit_src2_short): Likewise. (insert_nps_bitop_size_2b): Likewise. (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise. (RA_CHK): Define. (RB): Adjust. (RB_CHK): Define. (RC): Adjust. * arc-dis.c (print_insn_arc): Add LOAD and STORE class. * arc-tbl.h (div, divu): All instructions are DIVREM class. Change first insn argument to check for LP_COUNT usage. (rem): Likewise. (ld, ldd): All instructions are LOAD class. Change first insn argument to check for LP_COUNT usage. (st, std): All instructions are STORE class. (mac, mpy, dmac, mul, dmpy): All instructions are MPY class. Change first insn argument to check for LP_COUNT usage. (mov): All instructions are MOVE class. Change first insn argument to check for LP_COUNT usage. include/ 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE instruction classes.
1 parent ee881e5 commit abe7c33

10 files changed

Lines changed: 2390 additions & 2280 deletions

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‎gas/ChangeLog‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,12 @@
1+
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
2+
3+
* config/tc-arc.c (find_opcode_match): New function argument
4+
errmsg.
5+
(assemble_tokens): Collect and report the eventual error message
6+
found during opcode matching process.
7+
* testsuite/gas/arc/lpcount-err.s: New file.
8+
* testsuite/gas/arc/add_s-err.s: Update error message.
9+
110
2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
211
Amit Pawar <amit.pawar@amd.com>
312

‎gas/config/tc-arc.c‎

Lines changed: 20 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1710,7 +1710,8 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
17101710
int *pntok,
17111711
struct arc_flags *first_pflag,
17121712
int nflgs,
1713-
int *pcpumatch)
1713+
int *pcpumatch,
1714+
const char **errmsg)
17141715
{
17151716
const struct arc_opcode *opcode;
17161717
struct arc_opcode_hash_entry_iterator iter;
@@ -1765,7 +1766,7 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
17651766
{
17661767
case ARC_OPERAND_ADDRTYPE:
17671768
{
1768-
const char *errmsg = NULL;
1769+
*errmsg = NULL;
17691770

17701771
/* Check to be an address type. */
17711772
if (tok[tokidx].X_op != O_addrtype)
@@ -1776,8 +1777,8 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
17761777
address type. */
17771778
gas_assert (operand->insert != NULL);
17781779
(*operand->insert) (0, tok[tokidx].X_add_number,
1779-
&errmsg);
1780-
if (errmsg != NULL)
1780+
errmsg);
1781+
if (*errmsg != NULL)
17811782
goto match_failed;
17821783
}
17831784
break;
@@ -1803,11 +1804,11 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
18031804
/* Special handling? */
18041805
if (operand->insert)
18051806
{
1806-
const char *errmsg = NULL;
1807+
*errmsg = NULL;
18071808
(*operand->insert)(0,
18081809
regno (tok[tokidx].X_add_number),
1809-
&errmsg);
1810-
if (errmsg)
1810+
errmsg);
1811+
if (*errmsg)
18111812
{
18121813
if (operand->flags & ARC_OPERAND_IGNORE)
18131814
{
@@ -1923,11 +1924,11 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
19231924
{
19241925
if (operand->insert)
19251926
{
1926-
const char *errmsg = NULL;
1927+
*errmsg = NULL;
19271928
(*operand->insert)(0,
19281929
tok[tokidx].X_add_number,
1929-
&errmsg);
1930-
if (errmsg)
1930+
errmsg);
1931+
if (*errmsg)
19311932
goto match_failed;
19321933
}
19331934
else if (!(operand->flags & ARC_OPERAND_IGNORE))
@@ -1948,11 +1949,11 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
19481949
regs |= get_register (tok[tokidx].X_op_symbol);
19491950
if (operand->insert)
19501951
{
1951-
const char *errmsg = NULL;
1952+
*errmsg = NULL;
19521953
(*operand->insert)(0,
19531954
regs,
1954-
&errmsg);
1955-
if (errmsg)
1955+
errmsg);
1956+
if (*errmsg)
19561957
goto match_failed;
19571958
}
19581959
else
@@ -2326,6 +2327,7 @@ assemble_tokens (const char *opname,
23262327
bfd_boolean found_something = FALSE;
23272328
const struct arc_opcode_hash_entry *entry;
23282329
int cpumatch = 1;
2330+
const char *errmsg = NULL;
23292331

23302332
/* Search opcodes. */
23312333
entry = arc_find_opcode (opname);
@@ -2342,7 +2344,7 @@ assemble_tokens (const char *opname,
23422344
frag_now->fr_file, frag_now->fr_line, opname);
23432345
found_something = TRUE;
23442346
opcode = find_opcode_match (entry, tok, &ntok, pflags,
2345-
nflgs, &cpumatch);
2347+
nflgs, &cpumatch, &errmsg);
23462348
if (opcode != NULL)
23472349
{
23482350
struct arc_insn insn;
@@ -2356,7 +2358,10 @@ assemble_tokens (const char *opname,
23562358
if (found_something)
23572359
{
23582360
if (cpumatch)
2359-
as_bad (_("inappropriate arguments for opcode '%s'"), opname);
2361+
if (errmsg)
2362+
as_bad (_("%s for instruction '%s'"), errmsg, opname);
2363+
else
2364+
as_bad (_("inappropriate arguments for opcode '%s'"), opname);
23602365
else
23612366
as_bad (_("opcode '%s' not supported for target %s"), opname,
23622367
selected_cpu.name);

‎gas/testsuite/gas/arc/add_s-err.s‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
; { dg-do assemble { target arc*-*-* } }
55
; { dg-options "--mcpu=arc700" }
66
;; The following insns are accepted by ARCv2 only
7-
add_s r4,r4,-1 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
7+
add_s r4,r4,-1 ; { dg-error "Error: Register must be either r0-r3 or r12-r15 for instruction." }
88
add_s 0,0xAAAA5555,-1 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
99
add_s r0,r15,0x20 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
1010
add_s r1,r15,0x20 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }

‎gas/testsuite/gas/arc/lpcount-err.s‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
;; LP_COUNT register cannot be used with multi-cycle instructions such as:
2+
;; load, lr, multiply and divide.
3+
; { dg-do assemble { target arc*-*-* } }
4+
5+
.cpu HS
6+
7+
mpy lp_count,r0,r1 ; { dg-error "Error: LP_COUNT register cannot be used as destination register." }
8+
ld lp_count,[r2,1] ; { dg-error "Error: LP_COUNT register cannot be used as destination register." }
9+
div lp_count,r12,r1 ; { dg-error "Error: LP_COUNT register cannot be used as destination register." }

‎include/ChangeLog‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,8 @@
1+
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
2+
3+
* opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE
4+
instruction classes.
5+
16
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
27

38
* opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and

‎include/opcode/arc.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,17 +47,22 @@ typedef enum
4747
BMU,
4848
BRANCH,
4949
CONTROL,
50+
DIVREM,
5051
DPI,
5152
DSP,
5253
FLOAT,
5354
INVALID,
5455
JUMP,
5556
KERNEL,
57+
LOAD,
5658
LOGICAL,
5759
MEMORY,
60+
MOVE,
61+
MPY,
5862
NET,
5963
PROTOCOL_DECODE,
6064
PMU,
65+
STORE,
6166
XY
6267
} insn_class_t;
6368

‎opcodes/ChangeLog‎

Lines changed: 46 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,49 @@
1+
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
2+
3+
* arc-opc.c (insert_ra_chk): New function.
4+
(insert_rb_chk): Likewise.
5+
(insert_rad): Update text error message.
6+
(insert_rcd): Likewise.
7+
(insert_rhv2): Likewise.
8+
(insert_r0): Likewise.
9+
(insert_r1): Likewise.
10+
(insert_r2): Likewise.
11+
(insert_r3): Likewise.
12+
(insert_sp): Likewise.
13+
(insert_gp): Likewise.
14+
(insert_pcl): Likewise.
15+
(insert_blink): Likewise.
16+
(insert_ilink1): Likewise.
17+
(insert_ilink2): Likewise.
18+
(insert_ras): Likewise.
19+
(insert_rbs): Likewise.
20+
(insert_rcs): Likewise.
21+
(insert_simm3s): Likewise.
22+
(insert_rrange): Likewise.
23+
(insert_fpel): Likewise.
24+
(insert_blinkel): Likewise.
25+
(insert_pcel): Likewise.
26+
(insert_nps_3bit_dst): Likewise.
27+
(insert_nps_3bit_dst_short): Likewise.
28+
(insert_nps_3bit_src2_short): Likewise.
29+
(insert_nps_bitop_size_2b): Likewise.
30+
(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
31+
(RA_CHK): Define.
32+
(RB): Adjust.
33+
(RB_CHK): Define.
34+
(RC): Adjust.
35+
* arc-dis.c (print_insn_arc): Add LOAD and STORE class.
36+
* arc-tbl.h (div, divu): All instructions are DIVREM class.
37+
Change first insn argument to check for LP_COUNT usage.
38+
(rem): Likewise.
39+
(ld, ldd): All instructions are LOAD class. Change first insn
40+
argument to check for LP_COUNT usage.
41+
(st, std): All instructions are STORE class.
42+
(mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
43+
Change first insn argument to check for LP_COUNT usage.
44+
(mov): All instructions are MOVE class. Change first insn
45+
argument to check for LP_COUNT usage.
46+
147
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
248

349
* arc-dis.c (is_compatible_p): Remove function.

‎opcodes/arc-dis.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -750,8 +750,10 @@ arc_opcode_to_insn_type (const struct arc_opcode *opcode)
750750
insn_type = dis_branch;
751751
}
752752
break;
753+
case LOAD:
754+
case STORE:
753755
case MEMORY:
754-
insn_type = dis_dref; /* FIXME! DB indicates mov as memory! */
756+
insn_type = dis_dref;
755757
break;
756758
default:
757759
insn_type = dis_nonbranch;

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