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Add support for tilegx in gold.
 * configure.ac (ENABLE_GOLD): support tilegx* * configure: rebuild elfcpp: * tilegx.h: New file. * elfcpp.h: add EM_TILEGX. gold: * tilegx.cc: New file. * Makefile.am (TARGETSOURCES): Add tilegx.cc (ALL_TARGETOBJS): Add tilegx.$(OBJEXT) * configure.tgt: Add entries for tilegx*. * configure.ac: Likewise. * Makefile.in: Rebuild. * configure: Likewise. * testsuite/icf_safe_test.sh (arch_specific_safe_fold): Handle tilegx.
1 parent b132a67 commit 5c0b382

14 files changed

Lines changed: 5126 additions & 7 deletions

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‎ChangeLog‎

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@@ -1,3 +1,8 @@
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2012-09-15 Jiong Wang <jiwang@tilera.com>
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* configure.ac (ENABLE_GOLD): support tilegx*
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* configure: rebuild
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2012-09-14 David Edelsohn <dje.gcc@gmail.com>
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38
PR target/38607

‎configure‎

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@@ -2916,7 +2916,7 @@ case "${ENABLE_GOLD}" in
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if test "$is_elf" = "yes"; then
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# Check for target supported by gold.
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case "${target}" in
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i?86-*-* | x86_64-*-* | sparc*-*-* | powerpc*-*-* | arm*-*-*)
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i?86-*-* | x86_64-*-* | sparc*-*-* | powerpc*-*-* | arm*-*-* | tilegx*-*-*)
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configdirs="$configdirs gold"
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if test x${ENABLE_GOLD} = xdefault; then
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default_ld=gold

‎configure.ac‎

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@@ -328,7 +328,7 @@ case "${ENABLE_GOLD}" in
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if test "$is_elf" = "yes"; then
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# Check for target supported by gold.
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case "${target}" in
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i?86-*-* | x86_64-*-* | sparc*-*-* | powerpc*-*-* | arm*-*-*)
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i?86-*-* | x86_64-*-* | sparc*-*-* | powerpc*-*-* | arm*-*-* | tilegx*-*-*)
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configdirs="$configdirs gold"
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if test x${ENABLE_GOLD} = xdefault; then
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default_ld=gold

‎elfcpp/ChangeLog‎

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@@ -1,3 +1,8 @@
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2012-09-15 Jiong Wang <jiwang@tilera.com>
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* tilegx.h: New file.
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* elfcpp.h: add EM_TILEGX.
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16
2012-08-14 Alan Modra <amodra@gmail.com>
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38
* powerpc.h: Add more relocs.

‎elfcpp/elfcpp.h‎

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@@ -269,6 +269,7 @@ enum EM
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EM_UNICORE = 110,
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EM_ALTERA_NIOS2 = 113,
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EM_CRX = 114,
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EM_TILEGX = 191,
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// The Morph MT.
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EM_MT = 0x2530,
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// DLX.

‎elfcpp/tilegx.h‎

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// tilegx.h -- ELF definitions specific to EM_TILEGX -*- C++ -*-
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// Copyright 2012 Free Software Foundation, Inc.
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// Written by Jiong Wang (jiwang@tilera.com)
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// This file is part of elfcpp.
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// This program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Library General Public License
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// as published by the Free Software Foundation; either version 2, or
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// (at your option) any later version.
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// In addition to the permissions in the GNU Library General Public
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// License, the Free Software Foundation gives you unlimited
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// permission to link the compiled version of this file into
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// combinations with other programs, and to distribute those
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// combinations without any restriction coming from the use of this
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// file. (The Library Public License restrictions do apply in other
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// respects; for example, they cover modification of the file, and
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/// distribution when not linked into a combined executable.)
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// This program is distributed in the hope that it will be useful, but
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// WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Library General Public License for more details.
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// You should have received a copy of the GNU Library General Public
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// License along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
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// 02110-1301, USA.
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#ifndef ELFCPP_TILEGX_H
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#define ELFCPP_TILEGX_H
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namespace elfcpp
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{
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// Documentation is taken from
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// http://www.tilera.com/scm/docs/index.html
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enum
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{
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R_TILEGX_NONE = 0,
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R_TILEGX_64 = 1,
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R_TILEGX_32 = 2,
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R_TILEGX_16 = 3,
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R_TILEGX_8 = 4,
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R_TILEGX_64_PCREL = 5,
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R_TILEGX_32_PCREL = 6,
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R_TILEGX_16_PCREL = 7,
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R_TILEGX_8_PCREL = 8,
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R_TILEGX_HW0 = 9,
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R_TILEGX_HW1 = 10,
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R_TILEGX_HW2 = 11,
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R_TILEGX_HW3 = 12,
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R_TILEGX_HW0_LAST = 13,
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R_TILEGX_HW1_LAST = 14,
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R_TILEGX_HW2_LAST = 15,
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R_TILEGX_COPY = 16,
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R_TILEGX_GLOB_DAT = 17,
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R_TILEGX_JMP_SLOT = 18,
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R_TILEGX_RELATIVE = 19,
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R_TILEGX_BROFF_X1 = 20,
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R_TILEGX_JUMPOFF_X1 = 21,
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R_TILEGX_JUMPOFF_X1_PLT = 22,
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R_TILEGX_IMM8_X0 = 23,
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R_TILEGX_IMM8_Y0 = 24,
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R_TILEGX_IMM8_X1 = 25,
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R_TILEGX_IMM8_Y1 = 26,
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R_TILEGX_DEST_IMM8_X1 = 27,
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R_TILEGX_MT_IMM14_X1 = 28,
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R_TILEGX_MF_IMM14_X1 = 29,
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R_TILEGX_MMSTART_X0 = 30,
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R_TILEGX_MMEND_X0 = 31,
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R_TILEGX_SHAMT_X0 = 32,
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R_TILEGX_SHAMT_X1 = 33,
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R_TILEGX_SHAMT_Y0 = 34,
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R_TILEGX_SHAMT_Y1 = 35,
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R_TILEGX_IMM16_X0_HW0 = 36,
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R_TILEGX_IMM16_X1_HW0 = 37,
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R_TILEGX_IMM16_X0_HW1 = 38,
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R_TILEGX_IMM16_X1_HW1 = 39,
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R_TILEGX_IMM16_X0_HW2 = 40,
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R_TILEGX_IMM16_X1_HW2 = 41,
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R_TILEGX_IMM16_X0_HW3 = 42,
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R_TILEGX_IMM16_X1_HW3 = 43,
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R_TILEGX_IMM16_X0_HW0_LAST = 44,
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R_TILEGX_IMM16_X1_HW0_LAST = 45,
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R_TILEGX_IMM16_X0_HW1_LAST = 46,
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R_TILEGX_IMM16_X1_HW1_LAST = 47,
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R_TILEGX_IMM16_X0_HW2_LAST = 48,
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R_TILEGX_IMM16_X1_HW2_LAST = 49,
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R_TILEGX_IMM16_X0_HW0_PCREL = 50,
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R_TILEGX_IMM16_X1_HW0_PCREL = 51,
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R_TILEGX_IMM16_X0_HW1_PCREL = 52,
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R_TILEGX_IMM16_X1_HW1_PCREL = 53,
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R_TILEGX_IMM16_X0_HW2_PCREL = 54,
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R_TILEGX_IMM16_X1_HW2_PCREL = 55,
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R_TILEGX_IMM16_X0_HW3_PCREL = 56,
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R_TILEGX_IMM16_X1_HW3_PCREL = 57,
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R_TILEGX_IMM16_X0_HW0_LAST_PCREL = 58,
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R_TILEGX_IMM16_X1_HW0_LAST_PCREL = 59,
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R_TILEGX_IMM16_X0_HW1_LAST_PCREL = 60,
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R_TILEGX_IMM16_X1_HW1_LAST_PCREL = 61,
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R_TILEGX_IMM16_X0_HW2_LAST_PCREL = 62,
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R_TILEGX_IMM16_X1_HW2_LAST_PCREL = 63,
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R_TILEGX_IMM16_X0_HW0_GOT = 64,
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R_TILEGX_IMM16_X1_HW0_GOT = 65,
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R_TILEGX_IMM16_X0_HW0_PLT_PCREL = 66,
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R_TILEGX_IMM16_X1_HW0_PLT_PCREL = 67,
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R_TILEGX_IMM16_X0_HW1_PLT_PCREL = 68,
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R_TILEGX_IMM16_X1_HW1_PLT_PCREL = 69,
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R_TILEGX_IMM16_X0_HW2_PLT_PCREL = 70,
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R_TILEGX_IMM16_X1_HW2_PLT_PCREL = 71,
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R_TILEGX_IMM16_X0_HW0_LAST_GOT = 72,
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R_TILEGX_IMM16_X1_HW0_LAST_GOT = 73,
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R_TILEGX_IMM16_X0_HW1_LAST_GOT = 74,
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R_TILEGX_IMM16_X1_HW1_LAST_GOT = 75,
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R_TILEGX_IMM16_X0_HW0_TLS_GD = 78,
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R_TILEGX_IMM16_X1_HW0_TLS_GD = 79,
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R_TILEGX_IMM16_X0_HW0_TLS_LE = 80,
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R_TILEGX_IMM16_X1_HW0_TLS_LE = 81,
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R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE = 82,
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R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE = 83,
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R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE = 84,
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R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE = 85,
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R_TILEGX_IMM16_X0_HW0_LAST_TLS_GD = 86,
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R_TILEGX_IMM16_X1_HW0_LAST_TLS_GD = 87,
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R_TILEGX_IMM16_X0_HW1_LAST_TLS_GD = 88,
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R_TILEGX_IMM16_X1_HW1_LAST_TLS_GD = 89,
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R_TILEGX_IRELATIVE = 90,
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R_TILEGX_IMM16_X0_HW0_TLS_IE = 92,
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R_TILEGX_IMM16_X1_HW0_TLS_IE = 93,
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R_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL = 94,
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R_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL = 95,
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R_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL = 96,
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R_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL = 97,
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R_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL = 98,
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R_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL = 99,
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R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE = 100,
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R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE = 101,
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R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE = 102,
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R_TILEGX_IMM16_X1_HW1_LAST_TLS_IE = 103,
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R_TILEGX_TLS_DTPMOD64 = 106,
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R_TILEGX_TLS_DTPOFF64 = 107,
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R_TILEGX_TLS_TPOFF64 = 108,
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R_TILEGX_TLS_DTPMOD32 = 109,
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R_TILEGX_TLS_DTPOFF32 = 110,
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R_TILEGX_TLS_TPOFF32 = 111,
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R_TILEGX_TLS_GD_CALL = 112,
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R_TILEGX_IMM8_X0_TLS_GD_ADD = 113,
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R_TILEGX_IMM8_X1_TLS_GD_ADD = 114,
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R_TILEGX_IMM8_Y0_TLS_GD_ADD = 115,
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R_TILEGX_IMM8_Y1_TLS_GD_ADD = 116,
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R_TILEGX_TLS_IE_LOAD = 117,
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R_TILEGX_IMM8_X0_TLS_ADD = 118,
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R_TILEGX_IMM8_X1_TLS_ADD = 119,
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R_TILEGX_IMM8_Y0_TLS_ADD = 120,
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R_TILEGX_IMM8_Y1_TLS_ADD = 121,
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R_TILEGX_GNU_VTINHERIT = 128,
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R_TILEGX_GNU_VTENTRY = 129,
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R_TILEGX_NUM = 130
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};
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} // End namespace elfcpp.
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#endif // !defined(ELFCPP_TILEGX_H)

‎gold/ChangeLog‎

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2012-09-15 Jiong Wang <jiwang@tilera.com>
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* tilegx.cc: New file.
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* Makefile.am (TARGETSOURCES): Add tilegx.cc
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(ALL_TARGETOBJS): Add tilegx.$(OBJEXT)
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* configure.tgt: Add entries for tilegx*.
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* configure.ac: Likewise.
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* Makefile.in: Rebuild.
9+
* configure: Likewise.
10+
* testsuite/icf_safe_test.sh (arch_specific_safe_fold): Handle
11+
tilegx.
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2012-09-13 Alan Modra <amodra@gmail.com>
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315
* target-reloc.h (scan_relocs): Call scan.local for relocs

‎gold/Makefile.am‎

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EXTRA_DIST = yyscript.c yyscript.h
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TARGETSOURCES = \
147-
i386.cc x86_64.cc sparc.cc powerpc.cc arm.cc arm-reloc-property.cc
147+
i386.cc x86_64.cc sparc.cc powerpc.cc arm.cc arm-reloc-property.cc tilegx.cc
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149149
ALL_TARGETOBJS = \
150150
i386.$(OBJEXT) x86_64.$(OBJEXT) sparc.$(OBJEXT) powerpc.$(OBJEXT) \
151-
arm.$(OBJEXT) arm-reloc-property.$(OBJEXT)
151+
arm.$(OBJEXT) arm-reloc-property.$(OBJEXT) tilegx.$(OBJEXT)
152152

153153
libgold_a_SOURCES = $(CCFILES) $(HFILES) $(YFILES) $(DEFFILES)
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libgold_a_LIBADD = $(LIBOBJS)

‎gold/Makefile.in‎

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DEFFILES = arm-reloc.def
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EXTRA_DIST = yyscript.c yyscript.h
490490
TARGETSOURCES = \
491-
i386.cc x86_64.cc sparc.cc powerpc.cc arm.cc arm-reloc-property.cc
491+
i386.cc x86_64.cc sparc.cc powerpc.cc arm.cc arm-reloc-property.cc tilegx.cc
492492

493493
ALL_TARGETOBJS = \
494494
i386.$(OBJEXT) x86_64.$(OBJEXT) sparc.$(OBJEXT) powerpc.$(OBJEXT) \
495-
arm.$(OBJEXT) arm-reloc-property.$(OBJEXT)
495+
arm.$(OBJEXT) arm-reloc-property.$(OBJEXT) tilegx.$(OBJEXT)
496496

497497
libgold_a_SOURCES = $(CCFILES) $(HFILES) $(YFILES) $(DEFFILES)
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libgold_a_LIBADD = $(LIBOBJS)

‎gold/configure‎

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DEFAULT_TARGET_SPARC_FALSE=
34713471
fi
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3473+
if test "$targ_obj" = "tilegx"; then
3474+
DEFAULT_TARGET_TILEGX_TRUE=
3475+
DEFAULT_TARGET_TILEGX_FALSE='#'
3476+
else
3477+
DEFAULT_TARGET_TILEGX_TRUE='#'
3478+
DEFAULT_TARGET_TILEGX_FALSE=
3479+
fi
3480+
3481+
34733482
if test "$targ_obj" = "x86_64"; then
34743483
DEFAULT_TARGET_X86_64_TRUE=
34753484
DEFAULT_TARGET_X86_64_FALSE='#'

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