Skip to content

Commit 05b3d79

Browse files
author
Jim Wilson
committed
Fixes for addv and xtn2 instructions.
 sim/aarch64/ * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In case 3, call HALT_UNALLOC unconditionally. (do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to i + 2. Delete if on bias, change index to i + bias * X. sim/testsuite/sim/aarch64/ * addv.s: New. * xtn.s: New.
1 parent 11741d5 commit 05b3d79

5 files changed

Lines changed: 158 additions & 31 deletions

File tree

‎sim/aarch64/ChangeLog‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,11 @@
1+
2017-01-17 Jim Wilson <jim.wilson@linaro.org>
2+
3+
* simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
4+
aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In
5+
case 3, call HALT_UNALLOC unconditionally.
6+
(do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to
7+
i + 2. Delete if on bias, change index to i + bias * X.
8+
19
2017-01-09 Jim Wilson <jim.wilson@linaro.org>
210

311
* simulator.c (do_vec_UZP): Rewrite.

‎sim/aarch64/simulator.c‎

Lines changed: 16 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -3445,28 +3445,25 @@ do_vec_ADDV (sim_cpu *cpu)
34453445
case 0:
34463446
for (i = 0; i < (full ? 16 : 8); i++)
34473447
val += aarch64_get_vec_u8 (cpu, vm, i);
3448-
aarch64_set_reg_u64 (cpu, rd, NO_SP, val);
3448+
aarch64_set_vec_u64 (cpu, rd, 0, val);
34493449
return;
34503450

34513451
case 1:
34523452
for (i = 0; i < (full ? 8 : 4); i++)
34533453
val += aarch64_get_vec_u16 (cpu, vm, i);
3454-
aarch64_set_reg_u64 (cpu, rd, NO_SP, val);
3454+
aarch64_set_vec_u64 (cpu, rd, 0, val);
34553455
return;
34563456

34573457
case 2:
3458-
for (i = 0; i < (full ? 4 : 2); i++)
3458+
if (! full)
3459+
HALT_UNALLOC;
3460+
for (i = 0; i < 4; i++)
34593461
val += aarch64_get_vec_u32 (cpu, vm, i);
3460-
aarch64_set_reg_u64 (cpu, rd, NO_SP, val);
3462+
aarch64_set_vec_u64 (cpu, rd, 0, val);
34613463
return;
34623464

34633465
case 3:
3464-
if (! full)
3465-
HALT_UNALLOC;
3466-
val = aarch64_get_vec_u64 (cpu, vm, 0);
3467-
val += aarch64_get_vec_u64 (cpu, vm, 1);
3468-
aarch64_set_reg_u64 (cpu, rd, NO_SP, val);
3469-
return;
3466+
HALT_UNALLOC;
34703467
}
34713468
}
34723469

@@ -4206,33 +4203,21 @@ do_vec_XTN (sim_cpu *cpu)
42064203
switch (INSTR (23, 22))
42074204
{
42084205
case 0:
4209-
if (bias)
4210-
for (i = 0; i < 8; i++)
4211-
aarch64_set_vec_u8 (cpu, vd, i + 8,
4212-
aarch64_get_vec_u16 (cpu, vs, i) >> 8);
4213-
else
4214-
for (i = 0; i < 8; i++)
4215-
aarch64_set_vec_u8 (cpu, vd, i, aarch64_get_vec_u16 (cpu, vs, i));
4206+
for (i = 0; i < 8; i++)
4207+
aarch64_set_vec_u8 (cpu, vd, i + (bias * 8),
4208+
aarch64_get_vec_u16 (cpu, vs, i));
42164209
return;
42174210

42184211
case 1:
4219-
if (bias)
4220-
for (i = 0; i < 4; i++)
4221-
aarch64_set_vec_u16 (cpu, vd, i + 4,
4222-
aarch64_get_vec_u32 (cpu, vs, i) >> 16);
4223-
else
4224-
for (i = 0; i < 4; i++)
4225-
aarch64_set_vec_u16 (cpu, vd, i, aarch64_get_vec_u32 (cpu, vs, i));
4212+
for (i = 0; i < 4; i++)
4213+
aarch64_set_vec_u16 (cpu, vd, i + (bias * 4),
4214+
aarch64_get_vec_u32 (cpu, vs, i));
42264215
return;
42274216

42284217
case 2:
4229-
if (bias)
4230-
for (i = 0; i < 2; i++)
4231-
aarch64_set_vec_u32 (cpu, vd, i + 4,
4232-
aarch64_get_vec_u64 (cpu, vs, i) >> 32);
4233-
else
4234-
for (i = 0; i < 2; i++)
4235-
aarch64_set_vec_u32 (cpu, vd, i, aarch64_get_vec_u64 (cpu, vs, i));
4218+
for (i = 0; i < 2; i++)
4219+
aarch64_set_vec_u32 (cpu, vd, i + (bias * 2),
4220+
aarch64_get_vec_u64 (cpu, vs, i));
42364221
return;
42374222
}
42384223
}

‎sim/testsuite/sim/aarch64/ChangeLog‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,8 @@
1+
2017-01-17 Jim Wilson <jim.wilson@linaro.org>
2+
3+
* addv.s: New.
4+
* xtn.s: New.
5+
16
2017-01-09 Jim Wilson <jim.wilson@linaro.org>
27

38
* uzp.s: New.

‎sim/testsuite/sim/aarch64/addv.s‎

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,50 @@
1+
# mach: aarch64
2+
3+
# Check the add across vector instruction: addv.
4+
5+
.include "testutils.inc"
6+
7+
.data
8+
.align 4
9+
input:
10+
.word 0x04030201
11+
.word 0x08070605
12+
.word 0x0c0b0a09
13+
.word 0x100f0e0d
14+
15+
start
16+
adrp x0, input
17+
ldr q0, [x0, #:lo12:input]
18+
19+
addv b1, v0.8b
20+
mov x1, v1.d[0]
21+
cmp x1, #36
22+
bne .Lfailure
23+
24+
addv b1, v0.16b
25+
mov x1, v1.d[0]
26+
cmp x1, #136
27+
bne .Lfailure
28+
29+
addv h1, v0.4h
30+
mov x1, v1.d[0]
31+
mov x2, #5136
32+
cmp x1, x2
33+
bne .Lfailure
34+
35+
addv h1, v0.8h
36+
mov x1, v1.d[0]
37+
mov x2, #18496
38+
cmp x1, x2
39+
bne .Lfailure
40+
41+
addv s1, v0.4s
42+
mov x1, v1.d[0]
43+
mov x2, 8220
44+
movk x2, 0x2824, lsl 16
45+
cmp x1, x2
46+
bne .Lfailure
47+
48+
pass
49+
.Lfailure:
50+
fail

‎sim/testsuite/sim/aarch64/xtn.s‎

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,79 @@
1+
# mach: aarch64
2+
3+
# Check the extract narrow instructions: xtn, xtn2.
4+
5+
.include "testutils.inc"
6+
7+
.data
8+
.align 4
9+
input:
10+
.word 0x04030201
11+
.word 0x08070605
12+
.word 0x0c0b0a09
13+
.word 0x100f0e0d
14+
input2:
15+
.word 0x14131211
16+
.word 0x18171615
17+
.word 0x1c1b1a19
18+
.word 0x201f1e1d
19+
x16b:
20+
.word 0x07050301
21+
.word 0x0f0d0b09
22+
.word 0x17151311
23+
.word 0x1f1d1b19
24+
x8h:
25+
.word 0x06050201
26+
.word 0x0e0d0a09
27+
.word 0x16151211
28+
.word 0x1e1d1a19
29+
x4s:
30+
.word 0x04030201
31+
.word 0x0c0b0a09
32+
.word 0x14131211
33+
.word 0x1c1b1a19
34+
35+
start
36+
adrp x0, input
37+
ldr q0, [x0, #:lo12:input]
38+
adrp x0, input2
39+
ldr q1, [x0, #:lo12:input2]
40+
41+
xtn v2.8b, v0.8h
42+
xtn2 v2.16b, v1.8h
43+
mov x1, v2.d[0]
44+
mov x2, v2.d[1]
45+
adrp x3, x16b
46+
ldr x4, [x3, #:lo12:x16b]
47+
cmp x1, x4
48+
bne .Lfailure
49+
ldr x5, [x3, #:lo12:x16b+8]
50+
cmp x2, x5
51+
bne .Lfailure
52+
53+
xtn v2.4h, v0.4s
54+
xtn2 v2.8h, v1.4s
55+
mov x1, v2.d[0]
56+
mov x2, v2.d[1]
57+
adrp x3, x8h
58+
ldr x4, [x3, #:lo12:x8h]
59+
cmp x1, x4
60+
bne .Lfailure
61+
ldr x5, [x3, #:lo12:x8h+8]
62+
cmp x2, x5
63+
bne .Lfailure
64+
65+
xtn v2.2s, v0.2d
66+
xtn2 v2.4s, v1.2d
67+
mov x1, v2.d[0]
68+
mov x2, v2.d[1]
69+
adrp x3, x4s
70+
ldr x4, [x3, #:lo12:x4s]
71+
cmp x1, x4
72+
bne .Lfailure
73+
ldr x5, [x3, #:lo12:x4s+8]
74+
cmp x2, x5
75+
bne .Lfailure
76+
77+
pass
78+
.Lfailure:
79+
fail

0 commit comments

Comments
 (0)