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Copy pathsem.c
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3138 lines (2649 loc) · 80 KB
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/* Simulator instruction semantics for or1k32bf.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2019 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
#define WANT_CPU or1k32bf
#define WANT_CPU_OR1K32BF
#include "sim-main.h"
#include "cgen-mem.h"
#include "cgen-ops.h"
#undef GET_ATTR
#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
/* This is used so that we can compile two copies of the semantic code,
one with full feature support and one without that runs fast(er).
FAST_P, when desired, is defined on the command line, -DFAST_P=1. */
#if FAST_P
#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)
#undef CGEN_TRACE_RESULT
#define CGEN_TRACE_RESULT(cpu, abuf, name, type, val)
#else
#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
#endif
/* x-invalid: --invalid-- */
static SEM_PC
SEM_FN_NAME (or1k32bf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
/* Update the recorded pc in the cpu state struct.
Only necessary for WITH_SCACHE case, but to avoid the
conditional compilation .... */
SET_H_PC (pc);
/* Virtual insns have zero size. Overwrite vpc with address of next insn
using the default-insn-bitsize spec. When executing insns in parallel
we may want to queue the fault and continue execution. */
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
}
return vpc;
#undef FLD
}
/* x-after: --after-- */
static SEM_PC
SEM_FN_NAME (or1k32bf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
#if WITH_SCACHE_PBB_OR1K32BF
or1k32bf_pbb_after (current_cpu, sem_arg);
#endif
}
return vpc;
#undef FLD
}
/* x-before: --before-- */
static SEM_PC
SEM_FN_NAME (or1k32bf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
#if WITH_SCACHE_PBB_OR1K32BF
or1k32bf_pbb_before (current_cpu, sem_arg);
#endif
}
return vpc;
#undef FLD
}
/* x-cti-chain: --cti-chain-- */
static SEM_PC
SEM_FN_NAME (or1k32bf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
#if WITH_SCACHE_PBB_OR1K32BF
#ifdef DEFINE_SWITCH
vpc = or1k32bf_pbb_cti_chain (current_cpu, sem_arg,
pbb_br_type, pbb_br_npc);
BREAK (sem);
#else
/* FIXME: Allow provision of explicit ifmt spec in insn spec. */
vpc = or1k32bf_pbb_cti_chain (current_cpu, sem_arg,
CPU_PBB_BR_TYPE (current_cpu),
CPU_PBB_BR_NPC (current_cpu));
#endif
#endif
}
return vpc;
#undef FLD
}
/* x-chain: --chain-- */
static SEM_PC
SEM_FN_NAME (or1k32bf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
#if WITH_SCACHE_PBB_OR1K32BF
vpc = or1k32bf_pbb_chain (current_cpu, sem_arg);
#ifdef DEFINE_SWITCH
BREAK (sem);
#endif
#endif
}
return vpc;
#undef FLD
}
/* x-begin: --begin-- */
static SEM_PC
SEM_FN_NAME (or1k32bf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
#if WITH_SCACHE_PBB_OR1K32BF
#if defined DEFINE_SWITCH || defined FAST_P
/* In the switch case FAST_P is a constant, allowing several optimizations
in any called inline functions. */
vpc = or1k32bf_pbb_begin (current_cpu, FAST_P);
#else
#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
vpc = or1k32bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
#else
vpc = or1k32bf_pbb_begin (current_cpu, 0);
#endif
#endif
#endif
}
return vpc;
#undef FLD
}
/* l-j: l.j ${disp26} */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_j) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_j.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
{
USI opval = FLD (i_disp26);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
if (GET_H_SYS_CPUCFGR_ND ()) {
if (1)
SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
}
}
SEM_BRANCH_FINI (vpc);
return vpc;
#undef FLD
}
/* l-adrp: l.adrp $rD,${disp21} */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_adrp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_adrp.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
USI opval = FLD (i_disp21);
SET_H_GPR (FLD (f_r1), opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
#undef FLD
}
/* l-jal: l.jal ${disp26} */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_jal) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_j.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
USI opval = ADDSI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8)));
SET_H_GPR (((UINT) 9), opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
{
{
{
USI opval = FLD (i_disp26);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
if (GET_H_SYS_CPUCFGR_ND ()) {
if (1)
SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
}
}
}
SEM_BRANCH_FINI (vpc);
return vpc;
#undef FLD
}
/* l-jr: l.jr $rB */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_jr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
{
USI opval = GET_H_GPR (FLD (f_r3));
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
if (GET_H_SYS_CPUCFGR_ND ()) {
if (1)
SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
}
}
SEM_BRANCH_FINI (vpc);
return vpc;
#undef FLD
}
/* l-jalr: l.jalr $rB */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_jalr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
USI opval = ADDSI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8)));
SET_H_GPR (((UINT) 9), opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
{
{
{
USI opval = GET_H_GPR (FLD (f_r3));
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
if (GET_H_SYS_CPUCFGR_ND ()) {
if (1)
SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
}
}
}
SEM_BRANCH_FINI (vpc);
return vpc;
#undef FLD
}
/* l-bnf: l.bnf ${disp26} */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_bnf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_j.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
if (NOTSI (GET_H_SYS_SR_F ())) {
{
{
USI opval = FLD (i_disp26);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
} else {
if (GET_H_SYS_CPUCFGR_ND ()) {
{
{
USI opval = ADDSI (pc, 4);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
}
}
if (GET_H_SYS_CPUCFGR_ND ()) {
if (1)
SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
}
}
abuf->written = written;
SEM_BRANCH_FINI (vpc);
return vpc;
#undef FLD
}
/* l-bf: l.bf ${disp26} */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_bf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_j.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
if (GET_H_SYS_SR_F ()) {
{
{
USI opval = FLD (i_disp26);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
} else {
if (GET_H_SYS_CPUCFGR_ND ()) {
{
{
USI opval = ADDSI (pc, 4);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
}
}
if (GET_H_SYS_CPUCFGR_ND ()) {
if (1)
SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
}
}
abuf->written = written;
SEM_BRANCH_FINI (vpc);
return vpc;
#undef FLD
}
/* l-trap: l.trap ${uimm16} */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
or1k32bf_exception (current_cpu, pc, EXCEPT_TRAP);
return vpc;
#undef FLD
}
/* l-sys: l.sys ${uimm16} */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_sys) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
or1k32bf_exception (current_cpu, pc, EXCEPT_SYSCALL);
return vpc;
#undef FLD
}
/* l-msync: l.msync */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_msync) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
((void) 0); /*nop*/
return vpc;
#undef FLD
}
/* l-psync: l.psync */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_psync) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
((void) 0); /*nop*/
return vpc;
#undef FLD
}
/* l-csync: l.csync */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_csync) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
((void) 0); /*nop*/
return vpc;
#undef FLD
}
/* l-rfe: l.rfe */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_rfe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
or1k32bf_rfe (current_cpu);
return vpc;
#undef FLD
}
/* l-nop-imm: l.nop ${uimm16} */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_nop_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_mfspr.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
or1k32bf_nop (current_cpu, ZEXTSISI (FLD (f_uimm16)));
return vpc;
#undef FLD
}
/* l-movhi: l.movhi $rD,$uimm16 */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_movhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_mfspr.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
USI opval = SLLSI (ZEXTSISI (FLD (f_uimm16)), 16);
SET_H_GPR (FLD (f_r1), opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
#undef FLD
}
/* l-macrc: l.macrc $rD */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_macrc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_adrp.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
USI opval = GET_H_MAC_MACLO ();
SET_H_GPR (FLD (f_r1), opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
{
USI opval = 0;
SET_H_MAC_MACLO (opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
}
{
USI opval = 0;
SET_H_MAC_MACHI (opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
}
}
return vpc;
#undef FLD
}
/* l-mfspr: l.mfspr $rD,$rA,${uimm16} */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_mfspr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_mfspr.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
USI opval = or1k32bf_mfspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16))));
SET_H_GPR (FLD (f_r1), opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
#undef FLD
}
/* l-mtspr: l.mtspr $rA,$rB,${uimm16-split} */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_mtspr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_mtspr.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16_split))), GET_H_GPR (FLD (f_r3)));
return vpc;
#undef FLD
}
/* l-lwz: l.lwz $rD,${simm16}($rA) */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_lwz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
USI opval = ZEXTSISI (GETMEMUSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
SET_H_GPR (FLD (f_r1), opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
#undef FLD
}
/* l-lws: l.lws $rD,${simm16}($rA) */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_lws) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = EXTSISI (GETMEMSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
SET_H_GPR (FLD (f_r1), opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
#undef FLD
}
/* l-lwa: l.lwa $rD,${simm16}($rA) */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_lwa) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
USI opval = ZEXTSISI (GETMEMUSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
SET_H_GPR (FLD (f_r1), opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
{
BI opval = 1;
CPU (h_atomic_reserve) = opval;
CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
}
{
SI opval = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4);
CPU (h_atomic_address) = opval;
CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-address", 'x', opval);
}
}
return vpc;
#undef FLD
}
/* l-lbz: l.lbz $rD,${simm16}($rA) */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_lbz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
USI opval = ZEXTQISI (GETMEMUQI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1)));
SET_H_GPR (FLD (f_r1), opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
#undef FLD
}
/* l-lbs: l.lbs $rD,${simm16}($rA) */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_lbs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = EXTQISI (GETMEMQI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1)));
SET_H_GPR (FLD (f_r1), opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
#undef FLD
}
/* l-lhz: l.lhz $rD,${simm16}($rA) */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_lhz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
USI opval = ZEXTHISI (GETMEMUHI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2)));
SET_H_GPR (FLD (f_r1), opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
#undef FLD
}
/* l-lhs: l.lhs $rD,${simm16}($rA) */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_lhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = EXTHISI (GETMEMHI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2)));
SET_H_GPR (FLD (f_r1), opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
#undef FLD
}
/* l-sw: l.sw ${simm16-split}($rA),$rB */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_sw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sw.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI tmp_addr;
tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4);
{
USI opval = TRUNCSISI (GET_H_GPR (FLD (f_r3)));
SETMEMUSI (current_cpu, pc, tmp_addr, opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
{
BI opval = 0;
CPU (h_atomic_reserve) = opval;
written |= (1 << 4);
CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
}
}
}
abuf->written = written;
return vpc;
#undef FLD
}
/* l-sb: l.sb ${simm16-split}($rA),$rB */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_sb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sw.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI tmp_addr;
tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 1);
{
UQI opval = TRUNCSIQI (GET_H_GPR (FLD (f_r3)));
SETMEMUQI (current_cpu, pc, tmp_addr, opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
{
BI opval = 0;
CPU (h_atomic_reserve) = opval;
written |= (1 << 4);
CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
}
}
}
abuf->written = written;
return vpc;
#undef FLD
}
/* l-sh: l.sh ${simm16-split}($rA),$rB */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_sh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sw.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI tmp_addr;
tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 2);
{
UHI opval = TRUNCSIHI (GET_H_GPR (FLD (f_r3)));
SETMEMUHI (current_cpu, pc, tmp_addr, opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
{
BI opval = 0;
CPU (h_atomic_reserve) = opval;
written |= (1 << 4);
CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
}
}
}
abuf->written = written;
return vpc;
#undef FLD
}
/* l-swa: l.swa ${simm16-split}($rA),$rB */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_swa) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sw.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI tmp_addr;
BI tmp_flag;
tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4);
{
USI opval = ANDBI (CPU (h_atomic_reserve), EQSI (tmp_addr, CPU (h_atomic_address)));
SET_H_SYS_SR_F (opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
if (GET_H_SYS_SR_F ()) {
{
USI opval = TRUNCSISI (GET_H_GPR (FLD (f_r3)));
SETMEMUSI (current_cpu, pc, tmp_addr, opval);
written |= (1 << 7);
CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
}
{
BI opval = 0;
CPU (h_atomic_reserve) = opval;
CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
}
}
abuf->written = written;
return vpc;
#undef FLD
}
/* l-sll: l.sll $rD,$rA,$rB */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
USI opval = SLLSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
#undef FLD
}
/* l-slli: l.slli $rD,$rA,${uimm6} */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_slli.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
USI opval = SLLSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
SET_H_GPR (FLD (f_r1), opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}