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/* mips.h. Mips opcode list for GDB, the GNU debugger.
Copyright (C) 1993-2019 Free Software Foundation, Inc.
Contributed by Ralph Campbell and OSF
Commented and modified by Ian Lance Taylor, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version 3,
or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING3. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef _MIPS_H_
#define _MIPS_H_
#include "bfd.h"
#ifdef __cplusplus
extern "C" {
#endif
/* These are bit masks and shift counts to use to access the various
fields of an instruction. To retrieve the X field of an
instruction, use the expression
(i >> OP_SH_X) & OP_MASK_X
To set the same field (to j), use
i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
Make sure you use fields that are appropriate for the instruction,
of course.
The 'i' format uses OP, RS, RT and IMMEDIATE.
The 'j' format uses OP and TARGET.
The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
The 'b' format uses OP, RS, RT and DELTA.
The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
breakpoint instruction are not defined; Kane says the breakpoint
code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
only use ten bits). An optional two-operand form of break/sdbbp
allows the lower ten bits to be set too, and MIPS32 and later
architectures allow 20 bits to be set with a signal operand
(using CODE20).
The syscall instruction uses CODE20.
The general coprocessor instructions use COPZ. */
#define OP_MASK_OP 0x3f
#define OP_SH_OP 26
#define OP_MASK_RS 0x1f
#define OP_SH_RS 21
#define OP_MASK_FR 0x1f
#define OP_SH_FR 21
#define OP_MASK_FMT 0x1f
#define OP_SH_FMT 21
#define OP_MASK_BCC 0x7
#define OP_SH_BCC 18
#define OP_MASK_CODE 0x3ff
#define OP_SH_CODE 16
#define OP_MASK_CODE2 0x3ff
#define OP_SH_CODE2 6
#define OP_MASK_RT 0x1f
#define OP_SH_RT 16
#define OP_MASK_FT 0x1f
#define OP_SH_FT 16
#define OP_MASK_CACHE 0x1f
#define OP_SH_CACHE 16
#define OP_MASK_RD 0x1f
#define OP_SH_RD 11
#define OP_MASK_FS 0x1f
#define OP_SH_FS 11
#define OP_MASK_PREFX 0x1f
#define OP_SH_PREFX 11
#define OP_MASK_CCC 0x7
#define OP_SH_CCC 8
#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
#define OP_SH_CODE20 6
#define OP_MASK_SHAMT 0x1f
#define OP_SH_SHAMT 6
#define OP_MASK_EXTLSB OP_MASK_SHAMT
#define OP_SH_EXTLSB OP_SH_SHAMT
#define OP_MASK_STYPE OP_MASK_SHAMT
#define OP_SH_STYPE OP_SH_SHAMT
#define OP_MASK_FD 0x1f
#define OP_SH_FD 6
#define OP_MASK_TARGET 0x3ffffff
#define OP_SH_TARGET 0
#define OP_MASK_COPZ 0x1ffffff
#define OP_SH_COPZ 0
#define OP_MASK_IMMEDIATE 0xffff
#define OP_SH_IMMEDIATE 0
#define OP_MASK_DELTA 0xffff
#define OP_SH_DELTA 0
#define OP_MASK_FUNCT 0x3f
#define OP_SH_FUNCT 0
#define OP_MASK_SPEC 0x3f
#define OP_SH_SPEC 0
#define OP_SH_LOCC 8 /* FP condition code. */
#define OP_SH_HICC 18 /* FP condition code. */
#define OP_MASK_CC 0x7
#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
#define OP_MASK_COP1NORM 0x1 /* a single bit. */
#define OP_SH_COP1SPEC 21 /* COP1 encodings. */
#define OP_MASK_COP1SPEC 0xf
#define OP_MASK_COP1SCLR 0x4
#define OP_MASK_COP1CMP 0x3
#define OP_SH_COP1CMP 4
#define OP_SH_FORMAT 21 /* FP short format field. */
#define OP_MASK_FORMAT 0x7
#define OP_SH_TRUE 16
#define OP_MASK_TRUE 0x1
#define OP_SH_GE 17
#define OP_MASK_GE 0x01
#define OP_SH_UNSIGNED 16
#define OP_MASK_UNSIGNED 0x1
#define OP_SH_HINT 16
#define OP_MASK_HINT 0x1f
#define OP_SH_MMI 0 /* Multimedia (parallel) op. */
#define OP_MASK_MMI 0x3f
#define OP_SH_MMISUB 6
#define OP_MASK_MMISUB 0x1f
#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
#define OP_SH_PERFREG 1
#define OP_SH_SEL 0 /* Coprocessor select field. */
#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
#define OP_SH_CODE19 6 /* 19 bit wait code. */
#define OP_MASK_CODE19 0x7ffff
#define OP_SH_ALN 21
#define OP_MASK_ALN 0x7
#define OP_SH_VSEL 21
#define OP_MASK_VSEL 0x1f
#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
but 0x8-0xf don't select bytes. */
#define OP_SH_VECBYTE 22
#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
#define OP_SH_VECALIGN 21
#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
#define OP_SH_INSMSB 11
#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
#define OP_SH_EXTMSBD 11
/* MIPS DSP ASE */
#define OP_SH_DSPACC 11
#define OP_MASK_DSPACC 0x3
#define OP_SH_DSPACC_S 21
#define OP_MASK_DSPACC_S 0x3
#define OP_SH_DSPSFT 20
#define OP_MASK_DSPSFT 0x3f
#define OP_SH_DSPSFT_7 19
#define OP_MASK_DSPSFT_7 0x7f
#define OP_SH_SA3 21
#define OP_MASK_SA3 0x7
#define OP_SH_SA4 21
#define OP_MASK_SA4 0xf
#define OP_SH_IMM8 16
#define OP_MASK_IMM8 0xff
#define OP_SH_IMM10 16
#define OP_MASK_IMM10 0x3ff
#define OP_SH_WRDSP 11
#define OP_MASK_WRDSP 0x3f
#define OP_SH_RDDSP 16
#define OP_MASK_RDDSP 0x3f
#define OP_SH_BP 11
#define OP_MASK_BP 0x3
/* MIPS MT ASE */
#define OP_SH_MT_U 5
#define OP_MASK_MT_U 0x1
#define OP_SH_MT_H 4
#define OP_MASK_MT_H 0x1
#define OP_SH_MTACC_T 18
#define OP_MASK_MTACC_T 0x3
#define OP_SH_MTACC_D 13
#define OP_MASK_MTACC_D 0x3
/* MIPS MCU ASE */
#define OP_MASK_3BITPOS 0x7
#define OP_SH_3BITPOS 12
#define OP_MASK_OFFSET12 0xfff
#define OP_SH_OFFSET12 0
#define OP_OP_COP0 0x10
#define OP_OP_COP1 0x11
#define OP_OP_COP2 0x12
#define OP_OP_COP3 0x13
#define OP_OP_LWC1 0x31
#define OP_OP_LWC2 0x32
#define OP_OP_LWC3 0x33 /* a.k.a. pref */
#define OP_OP_LDC1 0x35
#define OP_OP_LDC2 0x36
#define OP_OP_LDC3 0x37 /* a.k.a. ld */
#define OP_OP_SWC1 0x39
#define OP_OP_SWC2 0x3a
#define OP_OP_SWC3 0x3b
#define OP_OP_SDC1 0x3d
#define OP_OP_SDC2 0x3e
#define OP_OP_SDC3 0x3f /* a.k.a. sd */
/* MIPS VIRT ASE */
#define OP_MASK_CODE10 0x3ff
#define OP_SH_CODE10 11
/* Values in the 'VSEL' field. */
#define MDMX_FMTSEL_IMM_QH 0x1d
#define MDMX_FMTSEL_IMM_OB 0x1e
#define MDMX_FMTSEL_VEC_QH 0x15
#define MDMX_FMTSEL_VEC_OB 0x16
/* UDI */
#define OP_SH_UDI1 6
#define OP_MASK_UDI1 0x1f
#define OP_SH_UDI2 6
#define OP_MASK_UDI2 0x3ff
#define OP_SH_UDI3 6
#define OP_MASK_UDI3 0x7fff
#define OP_SH_UDI4 6
#define OP_MASK_UDI4 0xfffff
/* Octeon */
#define OP_SH_BBITIND 16
#define OP_MASK_BBITIND 0x1f
#define OP_SH_CINSPOS 6
#define OP_MASK_CINSPOS 0x1f
#define OP_SH_CINSLM1 11
#define OP_MASK_CINSLM1 0x1f
#define OP_SH_SEQI 6
#define OP_MASK_SEQI 0x3ff
/* Loongson */
#define OP_SH_OFFSET_A 6
#define OP_MASK_OFFSET_A 0xff
#define OP_SH_OFFSET_B 3
#define OP_MASK_OFFSET_B 0xff
#define OP_SH_OFFSET_C 6
#define OP_MASK_OFFSET_C 0x1ff
#define OP_SH_RZ 0
#define OP_MASK_RZ 0x1f
#define OP_SH_FZ 0
#define OP_MASK_FZ 0x1f
/* Every MICROMIPSOP_X definition requires a corresponding OP_X
definition, and vice versa. This simplifies various parts
of the operand handling in GAS. The fields below only exist
in the microMIPS encoding, so define each one to have an empty
range. */
#define OP_MASK_TRAP 0
#define OP_SH_TRAP 0
#define OP_MASK_OFFSET10 0
#define OP_SH_OFFSET10 0
#define OP_MASK_RS3 0
#define OP_SH_RS3 0
#define OP_MASK_MB 0
#define OP_SH_MB 0
#define OP_MASK_MC 0
#define OP_SH_MC 0
#define OP_MASK_MD 0
#define OP_SH_MD 0
#define OP_MASK_ME 0
#define OP_SH_ME 0
#define OP_MASK_MF 0
#define OP_SH_MF 0
#define OP_MASK_MG 0
#define OP_SH_MG 0
#define OP_MASK_MH 0
#define OP_SH_MH 0
#define OP_MASK_MJ 0
#define OP_SH_MJ 0
#define OP_MASK_ML 0
#define OP_SH_ML 0
#define OP_MASK_MM 0
#define OP_SH_MM 0
#define OP_MASK_MN 0
#define OP_SH_MN 0
#define OP_MASK_MP 0
#define OP_SH_MP 0
#define OP_MASK_MQ 0
#define OP_SH_MQ 0
#define OP_MASK_IMMA 0
#define OP_SH_IMMA 0
#define OP_MASK_IMMB 0
#define OP_SH_IMMB 0
#define OP_MASK_IMMC 0
#define OP_SH_IMMC 0
#define OP_MASK_IMMF 0
#define OP_SH_IMMF 0
#define OP_MASK_IMMG 0
#define OP_SH_IMMG 0
#define OP_MASK_IMMH 0
#define OP_SH_IMMH 0
#define OP_MASK_IMMI 0
#define OP_SH_IMMI 0
#define OP_MASK_IMMJ 0
#define OP_SH_IMMJ 0
#define OP_MASK_IMML 0
#define OP_SH_IMML 0
#define OP_MASK_IMMM 0
#define OP_SH_IMMM 0
#define OP_MASK_IMMN 0
#define OP_SH_IMMN 0
#define OP_MASK_IMMO 0
#define OP_SH_IMMO 0
#define OP_MASK_IMMP 0
#define OP_SH_IMMP 0
#define OP_MASK_IMMQ 0
#define OP_SH_IMMQ 0
#define OP_MASK_IMMU 0
#define OP_SH_IMMU 0
#define OP_MASK_IMMW 0
#define OP_SH_IMMW 0
#define OP_MASK_IMMX 0
#define OP_SH_IMMX 0
#define OP_MASK_IMMY 0
#define OP_SH_IMMY 0
/* Enhanced VA Scheme */
#define OP_SH_EVAOFFSET 7
#define OP_MASK_EVAOFFSET 0x1ff
/* Enumerates the various types of MIPS operand. */
enum mips_operand_type {
/* Described by mips_int_operand. */
OP_INT,
/* Described by mips_mapped_int_operand. */
OP_MAPPED_INT,
/* Described by mips_msb_operand. */
OP_MSB,
/* Described by mips_reg_operand. */
OP_REG,
/* Like OP_REG, but can be omitted if the register is the same as the
previous operand. */
OP_OPTIONAL_REG,
/* Described by mips_reg_pair_operand. */
OP_REG_PAIR,
/* Described by mips_pcrel_operand. */
OP_PCREL,
/* A performance register. The field is 5 bits in size, but the supported
values are much more restricted. */
OP_PERF_REG,
/* The final operand in a microMIPS ADDIUSP instruction. It mostly acts
as a normal 9-bit signed offset that is multiplied by four, but there
are four special cases:
-2 * 4 => -258 * 4
-1 * 4 => -257 * 4
0 * 4 => 256 * 4
1 * 4 => 257 * 4. */
OP_ADDIUSP_INT,
/* The target of a (D)CLO or (D)CLZ instruction. The operand spans two
5-bit register fields, both of which must be set to the destination
register. */
OP_CLO_CLZ_DEST,
/* A register list for a microMIPS LWM or SWM instruction. The operand
size determines whether the 16-bit or 32-bit encoding is required. */
OP_LWM_SWM_LIST,
/* The register list for an emulated MIPS16 ENTRY or EXIT instruction. */
OP_ENTRY_EXIT_LIST,
/* The register list and frame size for a MIPS16 SAVE or RESTORE
instruction. */
OP_SAVE_RESTORE_LIST,
/* A 10-bit field VVVVVNNNNN used for octobyte and quadhalf instructions:
V Meaning
----- -------
0EEE0 8 copies of $vN[E], OB format
0EE01 4 copies of $vN[E], QH format
10110 all 8 elements of $vN, OB format
10101 all 4 elements of $vN, QH format
11110 8 copies of immediate N, OB format
11101 4 copies of immediate N, QH format. */
OP_MDMX_IMM_REG,
/* A register operand that must match the destination register. */
OP_REPEAT_DEST_REG,
/* A register operand that must match the previous register. */
OP_REPEAT_PREV_REG,
/* $pc, which has no encoding in the architectural instruction. */
OP_PC,
/* $28, which has no encoding in the MIPS16e architectural instruction. */
OP_REG28,
/* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines
which. */
OP_VU0_SUFFIX,
/* Like OP_VU0_SUFFIX, but used when the operand's value has already
been set. Any suffix used here must match the previous value. */
OP_VU0_MATCH_SUFFIX,
/* An index selected by an integer, e.g. [1]. */
OP_IMM_INDEX,
/* An index selected by a register, e.g. [$2]. */
OP_REG_INDEX,
/* The operand spans two 5-bit register fields, both of which must be set to
the source register. */
OP_SAME_RS_RT,
/* Described by mips_prev_operand. */
OP_CHECK_PREV,
/* A register operand that must not be zero. */
OP_NON_ZERO_REG
};
/* Enumerates the types of MIPS register. */
enum mips_reg_operand_type {
/* General registers $0-$31. Software names like $at can also be used. */
OP_REG_GP,
/* Floating-point registers $f0-$f31. */
OP_REG_FP,
/* Coprocessor condition code registers $cc0-$cc7. FPU condition codes
can also be written $fcc0-$fcc7. */
OP_REG_CCC,
/* FPRs used in a vector capacity. They can be written $f0-$f31
or $v0-$v31, although the latter form is not used for the VR5400
vector instructions. */
OP_REG_VEC,
/* DSP accumulator registers $ac0-$ac3. */
OP_REG_ACC,
/* Coprocessor registers $0-$31. Mnemonic names like c0_cause can
also be used in some contexts. */
OP_REG_COPRO,
/* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can
also be used in some contexts. */
OP_REG_HW,
/* Floating-point registers $vf0-$vf31. */
OP_REG_VF,
/* Integer registers $vi0-$vi31. */
OP_REG_VI,
/* R5900 VU0 registers $I, $Q, $R and $ACC. */
OP_REG_R5900_I,
OP_REG_R5900_Q,
OP_REG_R5900_R,
OP_REG_R5900_ACC,
/* MSA registers $w0-$w31. */
OP_REG_MSA,
/* MSA control registers $0-$31. */
OP_REG_MSA_CTRL
};
/* Base class for all operands. */
struct mips_operand
{
/* The type of the operand. */
enum mips_operand_type type;
/* The operand occupies SIZE bits of the instruction, starting at LSB. */
unsigned short size;
unsigned short lsb;
};
/* Describes an integer operand with a regular encoding pattern. */
struct mips_int_operand
{
struct mips_operand root;
/* The low ROOT.SIZE bits of MAX_VAL encodes (MAX_VAL + BIAS) << SHIFT.
The cyclically previous field value encodes 1 << SHIFT less than that,
and so on. E.g.
- for { { T, 4, L }, 14, 0, 0 }, field values 0...14 encode themselves,
but 15 encodes -1.
- { { T, 8, L }, 127, 0, 2 } is a normal signed 8-bit operand that is
shifted left two places.
- { { T, 3, L }, 8, 0, 0 } is a normal unsigned 3-bit operand except
that 0 encodes 8.
- { { ... }, 0, 1, 3 } means that N encodes (N + 1) << 3. */
unsigned int max_val;
int bias;
unsigned int shift;
/* True if the operand should be printed as hex rather than decimal. */
bfd_boolean print_hex;
};
/* Uses a lookup table to describe a small integer operand. */
struct mips_mapped_int_operand
{
struct mips_operand root;
/* Maps each encoding value to the integer that it represents. */
const int *int_map;
/* True if the operand should be printed as hex rather than decimal. */
bfd_boolean print_hex;
};
/* An operand that encodes the most significant bit position of a bitfield.
Given a bitfield that spans bits [MSB, LSB], some operands of this type
encode MSB directly while others encode MSB - LSB. Each operand of this
type is preceded by an integer operand that specifies LSB.
The assembly form varies between instructions. For some instructions,
such as EXT, the operand is written as the bitfield size. For others,
such as EXTS, it is written in raw MSB - LSB form. */
struct mips_msb_operand
{
struct mips_operand root;
/* The assembly-level operand encoded by a field value of 0. */
int bias;
/* True if the operand encodes MSB directly, false if it encodes
MSB - LSB. */
bfd_boolean add_lsb;
/* The maximum value of MSB + 1. */
unsigned int opsize;
};
/* Describes a single register operand. */
struct mips_reg_operand
{
struct mips_operand root;
/* The type of register. */
enum mips_reg_operand_type reg_type;
/* If nonnull, REG_MAP[N] gives the register associated with encoding N,
otherwise the encoding is the same as the register number. */
const unsigned char *reg_map;
};
/* Describes an operand that which must match a condition based on the
previous operand. */
struct mips_check_prev_operand
{
struct mips_operand root;
bfd_boolean greater_than_ok;
bfd_boolean less_than_ok;
bfd_boolean equal_ok;
bfd_boolean zero_ok;
};
/* Describes an operand that encodes a pair of registers. */
struct mips_reg_pair_operand
{
struct mips_operand root;
/* The type of register. */
enum mips_reg_operand_type reg_type;
/* Encoding N represents REG1_MAP[N], REG2_MAP[N]. */
unsigned char *reg1_map;
unsigned char *reg2_map;
};
/* Describes an operand that is calculated relative to a base PC.
The base PC is usually the address of the following instruction,
but the rules for MIPS16 instructions like ADDIUPC are more complicated. */
struct mips_pcrel_operand
{
/* Encodes the offset. */
struct mips_int_operand root;
/* The low ALIGN_LOG2 bits of the base PC are cleared to give PC',
which is then added to the offset encoded by ROOT. */
unsigned int align_log2 : 8;
/* If INCLUDE_ISA_BIT, the ISA bit of the original base PC is then
reinstated. This is true for jumps and branches and false for
PC-relative data instructions. */
unsigned int include_isa_bit : 1;
/* If FLIP_ISA_BIT, the ISA bit of the result is inverted.
This is true for JALX and false otherwise. */
unsigned int flip_isa_bit : 1;
};
/* Return true if the assembly syntax allows OPERAND to be omitted. */
static inline bfd_boolean
mips_optional_operand_p (const struct mips_operand *operand)
{
return (operand->type == OP_OPTIONAL_REG
|| operand->type == OP_REPEAT_PREV_REG);
}
/* Return a version of INSN in which the field specified by OPERAND
has value UVAL. */
static inline unsigned int
mips_insert_operand (const struct mips_operand *operand, unsigned int insn,
unsigned int uval)
{
unsigned int mask;
mask = (1 << operand->size) - 1;
insn &= ~(mask << operand->lsb);
insn |= (uval & mask) << operand->lsb;
return insn;
}
/* Extract OPERAND from instruction INSN. */
static inline unsigned int
mips_extract_operand (const struct mips_operand *operand, unsigned int insn)
{
return (insn >> operand->lsb) & ((1 << operand->size) - 1);
}
/* UVAL is the value encoded by OPERAND. Return it in signed form. */
static inline int
mips_signed_operand (const struct mips_operand *operand, unsigned int uval)
{
unsigned int sign_bit, mask;
mask = (1 << operand->size) - 1;
sign_bit = 1 << (operand->size - 1);
return ((uval + sign_bit) & mask) - sign_bit;
}
/* Return the integer that OPERAND encodes as UVAL. */
static inline int
mips_decode_int_operand (const struct mips_int_operand *operand,
unsigned int uval)
{
uval |= (operand->max_val - uval) & -(1 << operand->root.size);
uval += operand->bias;
uval <<= operand->shift;
return uval;
}
/* Return the maximum value that can be encoded by OPERAND. */
static inline int
mips_int_operand_max (const struct mips_int_operand *operand)
{
return (operand->max_val + operand->bias) << operand->shift;
}
/* Return the minimum value that can be encoded by OPERAND. */
static inline int
mips_int_operand_min (const struct mips_int_operand *operand)
{
unsigned int mask;
mask = (1 << operand->root.size) - 1;
return mips_int_operand_max (operand) - (mask << operand->shift);
}
/* Return the register that OPERAND encodes as UVAL. */
static inline int
mips_decode_reg_operand (const struct mips_reg_operand *operand,
unsigned int uval)
{
if (operand->reg_map)
uval = operand->reg_map[uval];
return uval;
}
/* PC-relative operand OPERAND has value UVAL and is relative to BASE_PC.
Return the address that it encodes. */
static inline bfd_vma
mips_decode_pcrel_operand (const struct mips_pcrel_operand *operand,
bfd_vma base_pc, unsigned int uval)
{
bfd_vma addr;
addr = base_pc & -(1 << operand->align_log2);
addr += mips_decode_int_operand (&operand->root, uval);
if (operand->include_isa_bit)
addr |= base_pc & 1;
if (operand->flip_isa_bit)
addr ^= 1;
return addr;
}
/* This structure holds information for a particular instruction. */
struct mips_opcode
{
/* The name of the instruction. */
const char *name;
/* A string describing the arguments for this instruction. */
const char *args;
/* The basic opcode for the instruction. When assembling, this
opcode is modified by the arguments to produce the actual opcode
that is used. If pinfo is INSN_MACRO, then this is 0. */
unsigned long match;
/* If pinfo is not INSN_MACRO, then this is a bit mask for the
relevant portions of the opcode when disassembling. If the
actual opcode anded with the match field equals the opcode field,
then we have found the correct instruction. If pinfo is
INSN_MACRO, then this field is the macro identifier. */
unsigned long mask;
/* For a macro, this is INSN_MACRO. Otherwise, it is a collection
of bits describing the instruction, notably any relevant hazard
information. */
unsigned long pinfo;
/* A collection of additional bits describing the instruction. */
unsigned long pinfo2;
/* A collection of bits describing the instruction sets of which this
instruction or macro is a member. */
unsigned long membership;
/* A collection of bits describing the ASE of which this instruction
or macro is a member. */
unsigned long ase;
/* A collection of bits describing the instruction sets of which this
instruction or macro is not a member. */
unsigned long exclusions;
};
/* Return true if MO is an instruction that requires 32-bit encoding. */
static inline bfd_boolean
mips_opcode_32bit_p (const struct mips_opcode *mo)
{
return mo->mask >> 16 != 0;
}
/* These are the characters which may appear in the args field of an
instruction. They appear in the order in which the fields appear
when the instruction is used. Commas and parentheses in the args
string are ignored when assembling, and written into the output
when disassembling.
Each of these characters corresponds to a mask field defined above.
"1" 5 bit sync type (OP_*_STYPE)
"<" 5 bit shift amount (OP_*_SHAMT)
">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
"a" 26 bit target address (OP_*_TARGET)
"+i" likewise, but flips bit 0
"b" 5 bit base register (OP_*_RS)
"c" 10 bit breakpoint code (OP_*_CODE)
"d" 5 bit destination register specifier (OP_*_RD)
"h" 5 bit prefx hint (OP_*_PREFX)
"i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
"j" 16 bit signed immediate (OP_*_DELTA)
"k" 5 bit cache opcode in target register position (OP_*_CACHE)
"o" 16 bit signed offset (OP_*_DELTA)
"p" 16 bit PC relative branch target address (OP_*_DELTA)
"q" 10 bit extra breakpoint code (OP_*_CODE2)
"r" 5 bit same register used as both source and target (OP_*_RS)
"s" 5 bit source register specifier (OP_*_RS)
"t" 5 bit target register (OP_*_RT)
"u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
"v" 5 bit same register used as both source and destination (OP_*_RS)
"w" 5 bit same register used as both target and destination (OP_*_RT)
"U" 5 bit same destination register in both OP_*_RD and OP_*_RT
(used by clo and clz)
"C" 25 bit coprocessor function code (OP_*_COPZ)
"B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
"J" 19 bit wait function code (OP_*_CODE19)
"x" accept and ignore register name
"z" must be zero register
"K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
"+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for
microMIPS compatibility).
Enforces: 0 <= pos < 32.
"+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
Requires that "+A" or "+E" occur first to set position.
Enforces: 0 < (pos+size) <= 32.
"+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
Requires that "+A" or "+E" occur first to set position.
Enforces: 0 < (pos+size) <= 32.
(Also used by "dext" w/ different limits, but limits for
that are checked by the M_DEXT macro.)
"+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
Enforces: 32 <= pos < 64.
"+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
Requires that "+A" or "+E" occur first to set position.
Enforces: 32 < (pos+size) <= 64.
"+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
Requires that "+A" or "+E" occur first to set position.
Enforces: 32 < (pos+size) <= 64.
"+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
Requires that "+A" or "+E" occur first to set position.
Enforces: 32 < (pos+size) <= 64.
Floating point instructions:
"D" 5 bit destination register (OP_*_FD)
"M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
"N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
"S" 5 bit fs source 1 register (OP_*_FS)
"T" 5 bit ft source 2 register (OP_*_FT)
"R" 5 bit fr source 3 register (OP_*_FR)
"V" 5 bit same register used as floating source and destination (OP_*_FS)
"W" 5 bit same register used as floating target and destination (OP_*_FT)
Coprocessor instructions:
"E" 5 bit target register (OP_*_RT)
"G" 5 bit destination register (OP_*_RD)
"H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
"P" 5 bit performance-monitor register (OP_*_PERFREG)
"e" 5 bit vector register byte specifier (OP_*_VECBYTE)
"%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
Macro instructions:
"A" General 32 bit expression
"I" 32 bit immediate (value placed in imm_expr).
"F" 64 bit floating point constant in .rdata
"L" 64 bit floating point constant in .lit8
"f" 32 bit floating point constant
"l" 32 bit floating point constant in .lit4
MDMX and VR5400 instruction operands (note that while these use the
FP register fields, the MDMX instructions accept both $fN and $vN names
for the registers):
"O" alignment offset (OP_*_ALN)
"Q" vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
"X" destination register (OP_*_FD)
"Y" source register (OP_*_FS)
"Z" source register (OP_*_FT)
R5900 VU0 Macromode instructions:
"+5" 5 bit floating point register (FD)
"+6" 5 bit floating point register (FS)
"+7" 5 bit floating point register (FT)
"+8" 5 bit integer register (FD)
"+9" 5 bit integer register (FS)
"+0" 5 bit integer register (FT)
"+K" match an existing 4-bit channel mask starting at bit 21
"+L" 2-bit channel index starting at bit 21
"+M" 2-bit channel index starting at bit 23
"+N" match an existing 2-bit channel index starting at bit 0
"+f" 15 bit immediate for VCALLMS
"+g" 5 bit signed immediate for VIADDI
"+m" $ACC register (syntax only)
"+q" $Q register (syntax only)
"+r" $R register (syntax only)
"+y" $I register (syntax only)
"#+" "++" decorator in ($reg++) sequence
"#-" "--" decorator in (--$reg) sequence
DSP ASE usage:
"2" 2 bit unsigned immediate for byte align (OP_*_BP)
"3" 3 bit unsigned immediate (OP_*_SA3)
"4" 4 bit unsigned immediate (OP_*_SA4)
"5" 8 bit unsigned immediate (OP_*_IMM8)
"6" 5 bit unsigned immediate (OP_*_RS)
"7" 2 bit dsp accumulator register (OP_*_DSPACC)
"8" 6 bit unsigned immediate (OP_*_WRDSP)
"9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
"0" 6 bit signed immediate (OP_*_DSPSFT)
":" 7 bit signed immediate (OP_*_DSPSFT_7)
"'" 6 bit unsigned immediate (OP_*_RDDSP)
"@" 10 bit signed immediate (OP_*_IMM10)
MT ASE usage:
"!" 1 bit usermode flag (OP_*_MT_U)
"$" 1 bit load high flag (OP_*_MT_H)
"*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
"&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
"g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
"+t" 5 bit coprocessor 0 destination register (OP_*_RT)
MCU ASE usage:
"~" 12 bit offset (OP_*_OFFSET12)
"\" 3 bit position for aset and aclr (OP_*_3BITPOS)
VIRT ASE usage:
"+J" 10-bit hypcall code (OP_*CODE10)
UDI immediates:
"+1" UDI immediate bits 6-10
"+2" UDI immediate bits 6-15
"+3" UDI immediate bits 6-20
"+4" UDI immediate bits 6-25
Octeon:
"+x" Bit index field of bbit. Enforces: 0 <= index < 32.
"+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64,
otherwise skips to next candidate.
"+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
"+P" Position field of cins/exts aliasing cins32/exts32. Matches if
32 <= pos < 64, otherwise skips to next candidate.
"+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512.
"+s" Length-minus-one field of cins32/exts32. Requires msb position
of the field to be <= 31.
"+S" Length-minus-one field of cins/exts. Requires msb position
of the field to be <= 63.
Loongson-ext ASE:
"+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A)
"+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B)
"+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C)
"+z" 5-bit rz register (OP_*_RZ)
"+Z" 5-bit fz register (OP_*_FZ)
interAptiv MR2:
"-m" register list for SAVE/RESTORE instruction
Enhanced VA Scheme:
"+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET)
MSA Extension:
"+d" 5-bit MSA register (FD)
"+e" 5-bit MSA register (FS)
"+h" 5-bit MSA register (FT)
"+k" 5-bit GPR at bit 6
"+l" 5-bit MSA control register at bit 6
"+n" 5-bit MSA control register at bit 11
"+o" 4-bit vector element index at bit 16
"+u" 3-bit vector element index at bit 16
"+v" 2-bit vector element index at bit 16
"+w" 1-bit vector element index at bit 16
"+T" (-512 .. 511) << 0 at bit 16
"+U" (-512 .. 511) << 1 at bit 16
"+V" (-512 .. 511) << 2 at bit 16
"+W" (-512 .. 511) << 3 at bit 16
"+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6
"+!" 3 bit unsigned bit position at bit 16
"+@" 4 bit unsigned bit position at bit 16
"+#" 6 bit unsigned bit position at bit 16
"+$" 5 bit unsigned immediate at bit 16
"+%" 5 bit signed immediate at bit 16
"+^" 10 bit signed immediate at bit 11
"+&" 0 vector element index
"+*" 5-bit register vector element index at bit 16
"+|" 8-bit mask at bit 16
MIPS R6:
"+:" 11-bit mask at bit 0
"+'" 26 bit PC relative branch target address
"+"" 21 bit PC relative branch target address
"+;" 5 bit same register in both OP_*_RS and OP_*_RT
"+I" 2bit unsigned bit position at bit 6
"+O" 3bit unsigned bit position at bit 6
"+R" must be program counter
"-a" (-262144 .. 262143) << 2 at bit 0
"-b" (-131072 .. 131071) << 3 at bit 0
"-d" Same as destination register GP
"-s" 5 bit source register specifier (OP_*_RS) not $0
"-t" 5 bit source register specifier (OP_*_RT) not $0
"-u" 5 bit source register specifier (OP_*_RT) greater than OP_*_RS
"-v" 5 bit source register specifier (OP_*_RT) not $0 not OP_*_RS
"-w" 5 bit source register specifier (OP_*_RT) less than or equal to OP_*_RS
"-x" 5 bit source register specifier (OP_*_RT) greater than or
equal to OP_*_RS
"-y" 5 bit source register specifier (OP_*_RT) not $0 less than OP_*_RS
"-A" symbolic offset (-262144 .. 262143) << 2 at bit 0
"-B" symbolic offset (-131072 .. 131071) << 3 at bit 0
GINV ASE usage:
"+\" 2 bit Global TLB invalidate type at bit 8
Other:
"()" parens surrounding optional value
"," separates operands
"+" Start of extension sequence.
Characters used so far, for quick reference when adding more: