Good evening,
We've been using ArrayFire for several years now with great results on the CUDA backend. We're trying to understand what the art of the possible is with ArrayFire and FPGA accelerator cards if the OpenCL backend is used.
Has anyone demonstrated the OpenCL backend working on an FPGA device such as a Xilinx PCIe card which advertises OpenCL support? Could this theoretically work if the OpenCL drivers for the card were installed and it was registered as a device on the machine? Would it support ArrayFire's JIT compilation and work in real-time in the way that the CUDA and CPU backends do on their respective hardware?
I suspect we're not the first people to ask these questions so we'd like to get some feedback to understand if this has been demonstrated before and what the limitations are. We recognize that OpenCL code will not be as efficient as writing manual VHDL or Verilog for these cards, but given the power efficiency of FPGAs it could still end up being advantageous to use them in this case.
Good evening,
We've been using ArrayFire for several years now with great results on the CUDA backend. We're trying to understand what the art of the possible is with ArrayFire and FPGA accelerator cards if the OpenCL backend is used.
Has anyone demonstrated the OpenCL backend working on an FPGA device such as a Xilinx PCIe card which advertises OpenCL support? Could this theoretically work if the OpenCL drivers for the card were installed and it was registered as a device on the machine? Would it support ArrayFire's JIT compilation and work in real-time in the way that the CUDA and CPU backends do on their respective hardware?
I suspect we're not the first people to ask these questions so we'd like to get some feedback to understand if this has been demonstrated before and what the limitations are. We recognize that OpenCL code will not be as efficient as writing manual VHDL or Verilog for these cards, but given the power efficiency of FPGAs it could still end up being advantageous to use them in this case.