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Copy pathInPlaceInterpreter.asm
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2626 lines (2319 loc) · 87.9 KB
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# Copyright (C) 2023-2025 Apple Inc. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY APPLE INC. AND ITS CONTRIBUTORS ``AS IS''
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR ITS CONTRIBUTORS
# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
# THE POSSIBILITY OF SUCH DAMAGE.
#
# IPInt: the Wasm in-place interpreter
#
# docs by Daniel Liu <daniel_liu4@apple.com>; started as a 2023 intern project
#
# Contents:
# 0. Documentation comments
# 1. Interpreter definitions
# 1.1: Register definitions
# 1.2: Constant definitions
# 2. Core interpreter macros
# 3. Helper interpreter macros
# 4. Interpreter entrypoints
# 5. Instruction implementation
#
##############################
# 1. Interpreter definitions #
##############################
# -------------------------
# 1.1: Register definitions
# -------------------------
# IPInt uses a number of core registers which store the interpreter's state:
# - PC: (Program Counter) IPInt's program counter. This records the interpreter's position in Wasm bytecode.
# - MC: (Metadata Counter) IPInt's metadata pointer. This records the corresponding position in generated metadata.
# - WI: (Wasm Instance) pointer to the current JSWebAssemblyInstance object. This is used for accessing
# function-specific data (callee-save).
# - MB: (Memory Base) pointer to the current Wasm memory base address (callee-save).
# - BC: (Bounds Check) the size of the current Wasm memory region, for bounds checking (callee-save).
#
# Locals are accessed at a constant offset from CFR:
# local[i] = CFR - IPIntLocalsBaseOffset - i * LocalSize
#
# Finally, we provide four "sc" (safe for call) registers which are guaranteed to not overlap with argument
# registers (sc0, sc1, sc2, sc3)
const alignIPInt = constexpr JSC::IPInt::alignIPInt
const alignArgumInt = constexpr JSC::IPInt::alignArgumInt
const alignUInt = constexpr JSC::IPInt::alignUInt
const alignMInt = constexpr JSC::IPInt::alignMInt
if ARM64 or ARM64E
const PC = csr7
const MC = csr6
# Wasm Pinned Registers
const WI = csr0
const MB = csr3
const BC = csr4
const sc0 = ws0
const sc1 = ws1
const sc2 = ws2
const sc3 = ws3
elsif X86_64
const PC = csr2
const MC = csr1
# Wasm Pinned Registers
const WI = csr0
const MB = csr3
const BC = csr4
const sc0 = ws0
const sc1 = ws1
const sc2 = csr3
const sc3 = csr4
elsif RISCV64
const PC = csr7
const MC = csr6
# Wasm Pinned Registers
const WI = csr0
const MB = csr3
const BC = csr4
const sc0 = ws0
const sc1 = ws1
const sc2 = csr9
const sc3 = csr10
else
const PC = invalidGPR
const MC = invalidGPR
# Wasm Pinned Registers
const WI = invalidGPR
const MB = invalidGPR
const BC = invalidGPR
const sc0 = invalidGPR
const sc1 = invalidGPR
const sc2 = invalidGPR
const sc3 = invalidGPR
end
# -------------------------
# 1.2: Constant definitions
# -------------------------
const PtrSize = constexpr (sizeof(void*))
const SlotSize = constexpr (sizeof(Register))
# amount of memory a local takes up on the stack (16 bytes for a v128)
const V128ISize = 16
const LocalSize = V128ISize
const StackValueSize = V128ISize
const WasmEntryPtrTag = constexpr WasmEntryPtrTag
# These must match the definition in GPRInfo.h
const wasmInstance = csr0
if X86_64 or ARM64 or ARM64E or RISCV64
const memoryBase = csr3
const boundsCheckingSize = csr4
else
const memoryBase = invalidGPR
const boundsCheckingSize = invalidGPR
end
const UnboxedWasmCalleeStackSlot = CallerFrame - constexpr Wasm::numberOfIPIntCalleeSaveRegisters * SlotSize - MachineRegisterSize
const WasmToJSScratchSpaceSize = constexpr Wasm::WasmToJSScratchSpaceSize
const WasmToJSCallableFunctionSlot = constexpr Wasm::WasmToJSCallableFunctionSlot
const WasmToJSIPIntReturnPCSlot = constexpr Wasm::WasmToJSIPIntReturnPCSlot
const WasmToJSIPIntMCSlot = constexpr Wasm::WasmToJSIPIntMCSlot
const IPIntCalleeSaveSpaceAsVirtualRegisters = constexpr Wasm::numberOfIPIntCalleeSaveRegisters + constexpr Wasm::numberOfIPIntInternalRegisters
const IPIntCalleeSaveSpaceStackAligned = (IPIntCalleeSaveSpaceAsVirtualRegisters * SlotSize + StackAlignment - 1) & ~StackAlignmentMask
# Offset from CFR to local[0]: local[i] = CFR - IPIntLocalsBaseOffset - i * LocalSize
const IPIntLocalsBaseOffset = IPIntCalleeSaveSpaceStackAligned + LocalSize
# Must match GPRInfo.h
if X86_64
const NumberOfWasmArgumentGPRs = 6
const NumberOfVolatileGPRs = NumberOfWasmArgumentGPRs + 2 // +2 for ws0 and ws1
elsif ARM64 or ARM64E or RISCV64
const NumberOfWasmArgumentGPRs = 8
const NumberOfVolatileGPRs = NumberOfWasmArgumentGPRs
else
error
end
const NumberOfWasmArgumentFPRs = 8
##############################
# 2. Core interpreter macros #
##############################
macro ipintOp(name, impl)
instructionLabel(name)
if TRACING
move cfr, a1
move PC, a2
move MC, a3
operationCall(macro() cCall4(_ipint_extern_trace) end)
end
impl()
end
# -----------------------------------
# 2.1: Core interpreter functionality
# -----------------------------------
# Get IPIntCallee object at startup
macro unboxWasmCallee(calleeBits, scratch)
andp ~(constexpr JSValue::NativeCalleeTag), calleeBits
leap WTFConfig + constexpr WTF::offsetOfWTFConfigLowestAccessibleAddress, scratch
loadp [scratch], scratch
addp scratch, calleeBits
end
# Tail-call dispatch
macro advancePC(amount)
addp amount, PC
end
macro advancePCByReg(amount)
addp amount, PC
end
macro advanceMC(amount)
addp amount, MC
end
macro advanceMCByReg(amount)
addp amount, MC
end
# Reads the byte at cursor and steps cursor past it; ARM64 does both in one post-indexed load.
macro loadbAndAdvance(cursor, dst)
if ARM64 or ARM64E
loadbinc [cursor], dst, 1
else
loadb [cursor], dst
addp 1, cursor
end
end
macro decodeLEBVarUInt(dst, cursor, scratch1, scratch2)
loadbAndAdvance(cursor, dst)
bbb dst, 0x80, .done
andq 0x7f, dst
move 7, scratch1
validateOpcodeConfig(scratch2)
.loop:
loadbAndAdvance(cursor, scratch2)
bbb scratch2, 0x80, .lastByte
andq 0x7f, scratch2
lshiftq scratch1, scratch2
orq scratch2, dst
addq 7, scratch1
jmp .loop
.lastByte:
# bit 7 already 0, no AND needed
lshiftq scratch1, scratch2
orq scratch2, dst
.done:
end
macro decodeLEBVarSInt32(dst, cursor, scratch1, scratch2)
loadbAndAdvance(cursor, dst)
bbb dst, 0x80, .singleByte
andq 0x7f, dst
move 7, scratch1
validateOpcodeConfig(scratch2)
.loop:
loadbAndAdvance(cursor, scratch2)
bbb scratch2, 0x80, .lastByte
andq 0x7f, scratch2
lshiftq scratch1, scratch2
orq scratch2, dst
addq 7, scratch1
jmp .loop
.lastByte:
# bit 7 already 0, no AND needed
# Check sign bit (0x40) BEFORE shifting
btiz scratch2, 0x40, .noSignExtend
lshiftq scratch1, scratch2
ori scratch2, dst # Ensure output is always upper zero-cleared.
addq 7, scratch1
# sign extend if shift < 32
bigteq scratch1, 32, .done
move -1, scratch2
lshiftq scratch1, scratch2
ori scratch2, dst # Ensure output is always upper zero-cleared.
jmp .done
.noSignExtend:
lshiftq scratch1, scratch2
ori scratch2, dst # Ensure output is always upper zero-cleared.
jmp .done
.singleByte:
lshifti 25, dst
rshifti 25, dst
.done:
end
macro decodeLEBVarSInt64(dst, cursor, scratch1, scratch2)
loadbAndAdvance(cursor, dst)
bbb dst, 0x80, .singleByte
andq 0x7f, dst
move 7, scratch1
validateOpcodeConfig(scratch2)
.loop:
loadbAndAdvance(cursor, scratch2)
bbb scratch2, 0x80, .lastByte
andq 0x7f, scratch2
lshiftq scratch1, scratch2
orq scratch2, dst
addq 7, scratch1
jmp .loop
.lastByte:
# bit 7 already 0, no AND needed
# Check sign bit (0x40) BEFORE shifting
btiz scratch2, 0x40, .noSignExtend
lshiftq scratch1, scratch2
orq scratch2, dst
addq 7, scratch1
# sign extend if shift < 64
bigteq scratch1, 64, .done
move -1, scratch2
lshiftq scratch1, scratch2
orq scratch2, dst
jmp .done
.noSignExtend:
lshiftq scratch1, scratch2
orq scratch2, dst
jmp .done
.singleByte:
lshiftq 57, dst
rshiftq 57, dst
.done:
end
macro skipLEB128(cursor, scratch)
.loop:
loadbAndAdvance(cursor, scratch)
bbaeq scratch, 0x80, .loop
end
macro checkStackOverflow(callee, scratch)
loadi Wasm::IPIntCallee::m_maxFrameSizeInV128[callee], scratch
mulp V128ISize, scratch
subp cfr, scratch, scratch
if not ADDRESS64
bpbeq scratch, cfr, .checkTrapAwareSoftStackLimit
handleDebuggerTrapIfNeededAndThrowWasmTrap(StackOverflow)
.checkTrapAwareSoftStackLimit:
end
bpbeq JSWebAssemblyInstance::m_stackMirror + StackManager::Mirror::m_trapAwareSoftStackLimit[wasmInstance], scratch, .stackHeightOK
.checkStack:
operationCallMayThrowPreservingVolatileRegisters(macro()
move scratch, a1
if X86_64
# On x86_64, callee parameter (ws0) gets clobbered by saveCallSiteIndex(). Reload from stack.
loadp UnboxedWasmCalleeStackSlot[cfr], a2
else
move callee, a2
end
move cfr, a3
cCall4(_ipint_extern_check_stack_and_vm_traps)
end)
.stackHeightOK:
end
# ----------------------
# 2.2: Code organization
# ----------------------
# Instruction labels
# Important Note: If you don't use the unaligned global label from C++ (in our case we use the
# labels in InPlaceInterpreter.cpp) then some linkers will still remove the definition which
# causes all kinds of problems.
macro instructionLabel(instrname)
aligned _ipint%instrname%_validate alignIPInt
_ipint%instrname%_validate:
_ipint%instrname%:
end
macro unimplementedInstruction(instrname)
instructionLabel(instrname)
validateOpcodeConfig(a0)
break
end
macro reservedOpcode(opcode)
unimplementedInstruction(_reserved_%opcode%)
end
macro atomicInstructionLabel(instrname)
aligned _ipint%instrname%_atomic_validate alignIPInt
_ipint%instrname%_atomic_validate:
_ipint%instrname%:
end
macro ipintAtomicOp(name, impl)
atomicInstructionLabel(name)
if TRACING
move cfr, a1
move PC, a2
move MC, a3
operationCall(macro() cCall4(_ipint_extern_trace) end)
end
impl()
end
macro reservedAtomicOpcode(opcode)
atomicInstructionLabel(_reserved_%opcode%)
validateOpcodeConfig(a0)
break
end
# ---------------------------------------
# 2.3: Interacting with the outside world
# ---------------------------------------
# Memory
macro ipintReloadMemory(scratch)
if ARM64 or ARM64E
loadpairq constexpr (JSWebAssemblyInstance::offsetOfCachedMemoryBaseSizePair(0))[wasmInstance], memoryBase, boundsCheckingSize
elsif X86_64
loadp constexpr (JSWebAssemblyInstance::offsetOfCachedMemoryBaseSizePair(0))[wasmInstance], memoryBase
loadp constexpr (JSWebAssemblyInstance::offsetOfCachedMemoryBaseSizePair(0) + 8)[wasmInstance], boundsCheckingSize
end
cagedPrimitiveMayBeNull(memoryBase, scratch)
end
# Call site tracking
macro saveCallSiteIndex()
if X86_64
loadp UnboxedWasmCalleeStackSlot[cfr], ws0
end
loadp Wasm::IPIntCallee::m_bytecode[ws0], t0
subp PC, t0, t0
storei t0, CallSiteIndex[cfr]
end
# Operation Calls
macro operationCall(fn)
validateOpcodeConfig(a0)
move wasmInstance, a0
push PC, MC
if ARM64 or ARM64E
# Save ws0 with padding for 16-byte alignment (PC+MC=16, ws0+pad=16, total=32)
subp MachineRegisterSize * 2, sp
storep ws0, [sp]
end
fn()
if ARM64 or ARM64E
loadp [sp], ws0
addp MachineRegisterSize * 2, sp
end
pop MC, PC
end
macro operationCallMayThrowImpl(fn, exceptionLabel)
saveCallSiteIndex()
validateOpcodeConfig(a0)
move wasmInstance, a0
push PC, MC
if ARM64 or ARM64E
# Save ws0 with padding for 16-byte alignment (PC+MC=16, ws0+ws0=16, total=32)
push ws0, ws0
end
fn()
bpeq r1, (constexpr JSC::IPInt::SlowPathExceptionTag), exceptionLabel
if ARM64 or ARM64E
loadp [sp], ws0
addp MachineRegisterSize * 2, sp
end
pop MC, PC
end
# The throwing half of operationCallMayThrowImpl. It lives out of line, once per value of
# sizeOfExtraRegistersPreserved, so that a handler calling an operation still fits in one
# alignIPInt-sized dispatch slot.
macro operationCallMayThrowExceptionTail(sizeOfExtraRegistersPreserved)
storei r0, ArgumentCountIncludingThis + LowWordOffset[cfr]
if ARM64 or ARM64E
move cfr, a1
move sp, a2
operationCall(macro() cCall3(_ipint_extern_handle_debugger_trap_if_needed) end)
addp sizeOfExtraRegistersPreserved + (4 * MachineRegisterSize), sp
elsif X86_64
addp sizeOfExtraRegistersPreserved + (2 * MachineRegisterSize), sp
end
jmp _wasm_throw_from_slow_path_trampoline
end
macro operationCallMayThrow(fn)
operationCallMayThrowImpl(fn, _ipint_operation_call_exception)
end
macro operationCallMayThrowPreservingVolatileRegisters(fn)
preserveWasmVolatileRegisters()
operationCallMayThrowImpl(fn, _ipint_operation_call_exception_preserving_volatile_registers)
restoreWasmVolatileRegisters()
end
# Exception handling
#
# debugger-aware trap. 2 instructions; heavy logic in _wasm_ipint_check_debugger_hook_and_throw_trap due to fixed-size IPInt dispatch slots.
macro handleDebuggerTrapIfNeededAndThrowWasmTrap(exception)
storei constexpr Wasm::ExceptionType::%exception%, ArgumentCountIncludingThis + LowWordOffset[cfr]
if ADDRESS64 and (ARM64 or ARM64E)
# Currently, only ARM64 and ARM64E with ADDRESS64 platforms support the WasmDebugger.
jmp _wasm_ipint_check_debugger_hook_and_throw_trap
else
jmp _wasm_throw_from_slow_path_trampoline
end
end
# OSR
macro ipintPrologueOSR(increment)
if WEBASSEMBLY_BBQJIT
loadp UnboxedWasmCalleeStackSlot[cfr], ws0
baddis increment, Wasm::IPIntCallee::m_tierUpCounter + Wasm::IPIntTierUpCounter::m_counter[ws0], .continue
preserveWasmArgumentRegisters()
ipintReloadMemory(t2)
push memoryBase, boundsCheckingSize
move cfr, a1
operationCall(macro() cCall2(_ipint_extern_prologue_osr) end)
move r0, ws0
pop boundsCheckingSize, memoryBase
restoreWasmArgumentRegisters()
btpz ws0, .continue
restoreIPIntRegisters()
restoreCallerPCAndCFR()
if ARM64E
leap _g_config, ws1
jmp JSCConfigGateMapOffset + (constexpr Gate::wasmOSREntry) * PtrSize[ws1], NativeToJITGatePtrTag # WasmEntryPtrTag
else
jmp ws0, WasmEntryPtrTag
end
.continue:
end # WEBASSEMBLY_BBQJIT
end
macro ipintLoopOSRCheck(increment, tierUpLabel)
if WEBASSEMBLY_BBQJIT
validateOpcodeConfig(ws0)
loadp UnboxedWasmCalleeStackSlot[cfr], ws0
baddis increment, Wasm::IPIntCallee::m_tierUpCounter + Wasm::IPIntTierUpCounter::m_counter[ws0], .continue
jmp tierUpLabel
.continue:
end
end
# The tier-up half of the loop opcode. It lives out of line so that the opcode still fits in one
# alignIPInt-sized dispatch slot; it either enters BBQ or falls through back into the interpreter.
macro ipintLoopOSRTierUp()
if WEBASSEMBLY_BBQJIT
move cfr, a1
move PC, a2
# Add 1 to the index due to WTF::UncheckedKeyHashMap not supporting 0 as a key
addq 1, a2
move sp, a3
operationCall(macro() cCall4(_ipint_extern_loop_osr) end)
btpz r1, .recover
restoreIPIntRegisters()
restoreCallerPCAndCFR()
move r0, a0
if ARM64E
move r1, ws0
leap _g_config, ws1
jmp JSCConfigGateMapOffset + (constexpr Gate::wasmOSREntry) * PtrSize[ws1], NativeToJITGatePtrTag # WasmEntryPtrTag
else
jmp r1, WasmEntryPtrTag
end
.recover:
loadp UnboxedWasmCalleeStackSlot[cfr], ws0
end
end
macro ipintEpilogueOSR(increment)
if WEBASSEMBLY_BBQJIT
loadp UnboxedWasmCalleeStackSlot[cfr], ws0
baddis increment, Wasm::IPIntCallee::m_tierUpCounter + Wasm::IPIntTierUpCounter::m_counter[ws0], .continue
move cfr, a1
operationCall(macro() cCall2(_ipint_extern_epilogue_osr) end)
.continue:
end
end
################################
# 3. Helper interpreter macros #
################################
macro argumINTAlign(instrname)
aligned _ipint_argumINT%instrname%_validate alignArgumInt
_ipint_argumINT%instrname%_validate:
_argumINT%instrname%:
end
macro mintAlign(instrname)
aligned _ipint_mint%instrname%_validate alignMInt
_ipint_mint%instrname%_validate:
_mint%instrname%:
end
macro uintAlign(instrname)
aligned _ipint_uint%instrname%_validate alignUInt
_ipint_uint%instrname%_validate:
_uint%instrname%:
end
macro forEachWasmArgumentGPR(fn)
if ARM64 or ARM64E
fn(0, wa0, wa1)
fn(2, wa2, wa3)
fn(4, wa4, wa5)
fn(6, wa6, wa7)
else
fn(0, wa0, wa1)
fn(2, wa2, wa3)
fn(4, wa4, wa5)
end
end
macro forEachWasmArgumentFPR(fn)
fn(0, wfa0, wfa1)
fn(2, wfa2, wfa3)
fn(4, wfa4, wfa5)
fn(6, wfa6, wfa7)
end
macro preserveWasmGPRArgumentRegistersImpl()
forEachWasmArgumentGPR(macro (index, gpr1, gpr2)
if ARM64 or ARM64E
storepairq gpr1, gpr2, index * MachineRegisterSize[sp]
else
storeq gpr1, (index + 0) * MachineRegisterSize[sp]
storeq gpr2, (index + 1) * MachineRegisterSize[sp]
end
end)
end
macro restoreWasmGPRArgumentRegistersImpl()
forEachWasmArgumentGPR(macro (index, gpr1, gpr2)
if ARM64 or ARM64E
loadpairq index * MachineRegisterSize[sp], gpr1, gpr2
else
loadq (index + 0) * MachineRegisterSize[sp], gpr1
loadq (index + 1) * MachineRegisterSize[sp], gpr2
end
end)
end
macro preserveWasmFPRArgumentRegistersImpl(fprBaseOffset)
forEachWasmArgumentFPR(macro (index, fpr1, fpr2)
if ARM64 or ARM64E
storepairv fpr1, fpr2, fprBaseOffset + index * VectorRegisterSize[sp]
elsif X86_64
storev fpr1, fprBaseOffset + (index + 0) * VectorRegisterSize[sp]
storev fpr2, fprBaseOffset + (index + 1) * VectorRegisterSize[sp]
else
stored fpr1, fprBaseOffset + (index + 0) * VectorRegisterSize[sp]
stored fpr2, fprBaseOffset + (index + 1) * VectorRegisterSize[sp]
end
end)
end
macro restoreWasmFPRArgumentRegistersImpl(fprBaseOffset)
forEachWasmArgumentFPR(macro (index, fpr1, fpr2)
if ARM64 or ARM64E
loadpairv fprBaseOffset + index * VectorRegisterSize[sp], fpr1, fpr2
elsif X86_64
loadv fprBaseOffset + (index + 0) * VectorRegisterSize[sp], fpr1
loadv fprBaseOffset + (index + 1) * VectorRegisterSize[sp], fpr2
else
loadd fprBaseOffset + (index + 0) * VectorRegisterSize[sp], fpr1
loadd fprBaseOffset + (index + 1) * VectorRegisterSize[sp], fpr2
end
end)
end
macro preserveWasmArgumentRegisters()
const gprStorageSize = NumberOfWasmArgumentGPRs * MachineRegisterSize
const fprStorageSize = NumberOfWasmArgumentFPRs * VectorRegisterSize
subp gprStorageSize + fprStorageSize, sp
preserveWasmGPRArgumentRegistersImpl()
preserveWasmFPRArgumentRegistersImpl(gprStorageSize)
end
macro preserveWasmVolatileRegisters()
const gprStorageSize = NumberOfVolatileGPRs * MachineRegisterSize
const fprStorageSize = NumberOfWasmArgumentFPRs * VectorRegisterSize
subp gprStorageSize + fprStorageSize, sp
preserveWasmGPRArgumentRegistersImpl()
if X86_64
storeq ws0, (NumberOfWasmArgumentGPRs + 0) * MachineRegisterSize[sp]
storeq ws1, (NumberOfWasmArgumentGPRs + 1) * MachineRegisterSize[sp]
end
preserveWasmFPRArgumentRegistersImpl(gprStorageSize)
end
macro restoreWasmArgumentRegisters()
const gprStorageSize = NumberOfWasmArgumentGPRs * MachineRegisterSize
const fprStorageSize = NumberOfWasmArgumentFPRs * VectorRegisterSize
restoreWasmGPRArgumentRegistersImpl()
restoreWasmFPRArgumentRegistersImpl(gprStorageSize)
addp gprStorageSize + fprStorageSize, sp
end
macro restoreWasmVolatileRegisters()
const gprStorageSize = NumberOfVolatileGPRs * MachineRegisterSize
const fprStorageSize = NumberOfWasmArgumentFPRs * VectorRegisterSize
restoreWasmGPRArgumentRegistersImpl()
if X86_64
loadq (NumberOfWasmArgumentGPRs + 0) * MachineRegisterSize[sp], ws0
loadq (NumberOfWasmArgumentGPRs + 1) * MachineRegisterSize[sp], ws1
end
restoreWasmFPRArgumentRegistersImpl(gprStorageSize)
addp gprStorageSize + fprStorageSize, sp
end
macro reloadMemoryRegistersFromInstance(instance, scratch1)
loadp constexpr (JSWebAssemblyInstance::offsetOfCachedMemoryBaseSizePair(0))[instance], memoryBase
loadp constexpr (JSWebAssemblyInstance::offsetOfCachedMemoryBaseSizePair(0) + sizeof(void*))[instance], boundsCheckingSize
cagedPrimitiveMayBeNull(memoryBase, scratch1) # If boundsCheckingSize is 0, pointer can be a nullptr.
end
macro throwException(exception)
storei constexpr Wasm::ExceptionType::%exception%, ArgumentCountIncludingThis + LowWordOffset[cfr]
jmp _wasm_throw_from_slow_path_trampoline
end
##############################
# 4. Interpreter entrypoints #
##############################
// If you change this, make sure to modify JSToWasm.cpp:createJSToWasmJITShared
op(js_to_wasm_wrapper_entry, macro ()
if not WEBASSEMBLY or C_LOOP
error
end
macro clobberVolatileRegisters()
if ARM64 or ARM64E
emit "movz x9, #0xBAD"
emit "movz x10, #0xBAD"
emit "movz x11, #0xBAD"
emit "movz x12, #0xBAD"
emit "movz x13, #0xBAD"
emit "movz x14, #0xBAD"
emit "movz x15, #0xBAD"
emit "movz x16, #0xBAD"
emit "movz x17, #0xBAD"
emit "movz x18, #0xBAD"
end
end
macro repeat(scratch, f)
move 0xBEEF, scratch
f(0)
f(1)
f(2)
f(3)
f(4)
f(5)
f(6)
f(7)
f(8)
f(9)
f(10)
f(11)
f(12)
f(13)
f(14)
f(15)
f(16)
f(17)
f(18)
f(19)
f(20)
f(21)
f(22)
f(23)
f(24)
f(25)
f(26)
f(27)
f(28)
f(29)
end
macro saveJSToWasmRegisters()
subp constexpr Wasm::JSToWasmCallee::SpillStackSpaceAligned, sp
if ARM64 or ARM64E
storepairq memoryBase, boundsCheckingSize, -2 * SlotSize[cfr]
storep wasmInstance, -3 * SlotSize[cfr]
elsif X86_64
# These must match the wasmToJS thunk, since the unwinder won't be able to tell who made this frame.
storep boundsCheckingSize, -1 * SlotSize[cfr]
storep memoryBase, -2 * SlotSize[cfr]
storep wasmInstance, -3 * SlotSize[cfr]
else
storei wasmInstance, -1 * SlotSize[cfr]
end
end
macro restoreJSToWasmRegisters()
if ARM64 or ARM64E
loadpairq -2 * SlotSize[cfr], memoryBase, boundsCheckingSize
loadp -3 * SlotSize[cfr], wasmInstance
elsif X86_64
loadp -1 * SlotSize[cfr], boundsCheckingSize
loadp -2 * SlotSize[cfr], memoryBase
loadp -3 * SlotSize[cfr], wasmInstance
else
loadi -1 * SlotSize[cfr], wasmInstance
end
addp constexpr Wasm::JSToWasmCallee::SpillStackSpaceAligned, sp
end
macro getWebAssemblyFunctionAndSetNativeCalleeAndInstance(webAssemblyFunctionOut, scratch)
# Re-load WebAssemblyFunction Callee
loadp Callee[cfr], webAssemblyFunctionOut
# Replace the WebAssemblyFunction Callee with our JSToWasm NativeCallee
loadp WebAssemblyFunction::m_boxedJSToWasmCallee[webAssemblyFunctionOut], scratch
storep scratch, Callee[cfr] # JSToWasmCallee
storep wasmInstance, CodeBlock[cfr]
end
if ASSERT_ENABLED
clobberVolatileRegisters()
end
tagReturnAddress sp
preserveCallerPCAndCFR()
saveJSToWasmRegisters()
# Load data from the entry callee
# This was written by doVMEntry
loadp Callee[cfr], ws0 # WebAssemblyFunction*
loadp WebAssemblyFunction::m_importableFunction + Wasm::WasmOrJSImportableFunction::targetInstance[ws0], wasmInstance
# Allocate stack space
loadi WebAssemblyFunction::m_frameSize[ws0], wa0
subp sp, wa0, wa0
if not ADDRESS64
bpa wa0, cfr, .stackOverflow
end
# We don't need to check m_trapAwareSoftStackLimit here because we'll end up
# entering the Wasm function, and its prologue will handle the trap check.
bpbeq wa0, JSWebAssemblyInstance::m_stackMirror + StackManager::Mirror::m_softStackLimit[wasmInstance], .stackOverflow
move wa0, sp
if ASSERT_ENABLED
repeat(wa0, macro (i)
storep wa0, -i * SlotSize + constexpr Wasm::JSToWasmCallee::RegisterStackSpaceAligned[sp]
end)
end
# a0 = current stack frame position
move sp, a0
# Save wasmInstance and put the correct Callee into the stack for building the frame
storep wasmInstance, CodeBlock[cfr]
loadp Callee[cfr], memoryBase
transferp WebAssemblyFunction::m_boxedJSToWasmCallee[ws0], Callee[cfr]
# Prepare frame
move ws0, a2
move cfr, a1
cCall3(_operationJSToWasmEntryWrapperBuildFrame)
# Restore Callee slot
storep memoryBase, Callee[cfr]
btpnz r1, .buildEntryFrameThrew
move r0, ws0
# Memory
if ARM64 or ARM64E
loadpairq constexpr (JSWebAssemblyInstance::offsetOfCachedMemoryBaseSizePair(0))[wasmInstance], memoryBase, boundsCheckingSize
elsif X86_64
loadp constexpr (JSWebAssemblyInstance::offsetOfCachedMemoryBaseSizePair(0))[wasmInstance], memoryBase
loadp constexpr (JSWebAssemblyInstance::offsetOfCachedMemoryBaseSizePair(0) + 8)[wasmInstance], boundsCheckingSize
end
cagedPrimitiveMayBeNull(memoryBase, wa0)
# Arguments
forEachWasmArgumentGPR(macro (index, gpr1, gpr2)
if ARM64 or ARM64E
loadpairq index * MachineRegisterSize[sp], gpr1, gpr2
else
loadq (index + 0) * MachineRegisterSize[sp], gpr1
loadq (index + 1) * MachineRegisterSize[sp], gpr2
end
end)
forEachWasmArgumentFPR(macro (index, fpr1, fpr2)
const base = NumberOfWasmArgumentGPRs * MachineRegisterSize
if ARM64 or ARM64E
loadpaird base + index * FPRRegisterSize[sp], fpr1, fpr2
else
loadd base + (index + 0) * FPRRegisterSize[sp], fpr1
loadd base + (index + 1) * FPRRegisterSize[sp], fpr2
end
end)
# Pop argument space values
addp constexpr Wasm::JSToWasmCallee::RegisterStackSpaceAligned, sp
if ASSERT_ENABLED
repeat(ws1, macro (i)
storep ws1, -i * SlotSize[sp]
end)
end
getWebAssemblyFunctionAndSetNativeCalleeAndInstance(ws1, ws0)
# Load callee entrypoint
loadp WebAssemblyFunction::m_importableFunction + Wasm::WasmOrJSImportableFunction::entrypointLoadLocation[ws1], ws0
loadp [ws0], ws0
# Set the callee's interpreter Wasm::Callee
transferp WebAssemblyFunction::m_importableFunction + Wasm::WasmOrJSImportableFunction::boxedCallee[ws1], constexpr (CallFrameSlot::callee - CallerFrameAndPC::sizeInRegisters) * 8[sp]
call ws0, WasmEntryPtrTag
if ASSERT_ENABLED
clobberVolatileRegisters()
end
# Don't restore SP to original position, stack results live above calleeSP.
# After a tail call the callee's frame may differ, so derive from actual SP.
# Just allocate register spill space below the callee's actual SP.
subp constexpr Wasm::JSToWasmCallee::RegisterStackSpaceAligned, sp
if ASSERT_ENABLED
repeat(ws0, macro (i)
storep ws0, -i * SlotSize + constexpr Wasm::JSToWasmCallee::RegisterStackSpaceAligned[sp]
end)
end
# Save return registers
# Return register are the same as the argument registers.
forEachWasmArgumentGPR(macro (index, gpr1, gpr2)
if ARM64 or ARM64E
storepairq gpr1, gpr2, index * MachineRegisterSize[sp]
else
storeq gpr1, (index + 0) * MachineRegisterSize[sp]
storeq gpr2, (index + 1) * MachineRegisterSize[sp]
end
end)
forEachWasmArgumentFPR(macro (index, fpr1, fpr2)
const base = NumberOfWasmArgumentGPRs * MachineRegisterSize
if ARM64 or ARM64E
storepaird fpr1, fpr2, base + index * FPRRegisterSize[sp]
else
stored fpr1, base + (index + 0) * FPRRegisterSize[sp]
stored fpr2, base + (index + 1) * FPRRegisterSize[sp]
end
end)
# Prepare frame
move sp, a0
move cfr, a1
cCall2(_operationJSToWasmEntryWrapperBuildReturnFrame)
btpnz r1, .unwind
# Clean up and return
restoreJSToWasmRegisters()
if ASSERT_ENABLED
clobberVolatileRegisters()
end
restoreCallerPCAndCFR()
ret
# We need to set our NativeCallee/instance here since haven't done it already and wasm_throw_from_slow_path_trampoline expects them.
.stackOverflow:
getWebAssemblyFunctionAndSetNativeCalleeAndInstance(ws1, ws0)
throwException(StackOverflow)
.buildEntryFrameThrew:
getWebAssemblyFunctionAndSetNativeCalleeAndInstance(ws1, ws0)
.unwind:
loadp JSWebAssemblyInstance::m_vm[wasmInstance], a0
copyCalleeSavesToVMEntryFrameCalleeSavesBuffer(a0, a1)