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dpgeorgedpgeorge
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py: Make macro names in assemblers consistent, and tidy up a bit.
1 parent d66e486 commit 0b610de

10 files changed

Lines changed: 302 additions & 335 deletions

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‎py/asmarm.c‎

Lines changed: 30 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -45,9 +45,8 @@ struct _asm_arm_t {
4545
byte *code_base;
4646
byte dummy_data[4];
4747

48-
uint max_num_labels;
49-
int *label_offsets;
50-
int num_locals;
48+
mp_uint_t max_num_labels;
49+
mp_uint_t *label_offsets;
5150
uint push_reglist;
5251
uint stack_adjust;
5352
};
@@ -57,7 +56,7 @@ asm_arm_t *asm_arm_new(uint max_num_labels) {
5756

5857
as = m_new0(asm_arm_t, 1);
5958
as->max_num_labels = max_num_labels;
60-
as->label_offsets = m_new(int, max_num_labels);
59+
as->label_offsets = m_new(mp_uint_t, max_num_labels);
6160

6261
return as;
6362
}
@@ -66,15 +65,15 @@ void asm_arm_free(asm_arm_t *as, bool free_code) {
6665
if (free_code) {
6766
MP_PLAT_FREE_EXEC(as->code_base, as->code_size);
6867
}
69-
68+
m_del(mp_uint_t, as->label_offsets, as->max_num_labels);
7069
m_del_obj(asm_arm_t, as);
7170
}
7271

7372
void asm_arm_start_pass(asm_arm_t *as, uint pass) {
7473
as->pass = pass;
7574
as->code_offset = 0;
7675
if (pass == ASM_ARM_PASS_COMPUTE) {
77-
memset(as->label_offsets, -1, as->max_num_labels * sizeof(int));
76+
memset(as->label_offsets, -1, as->max_num_labels * sizeof(mp_uint_t));
7877
}
7978
}
8079

@@ -127,7 +126,7 @@ STATIC void emit(asm_arm_t *as, uint op) {
127126

128127
// Insert word into instruction flow, add "ALWAYS" condition code
129128
STATIC void emit_al(asm_arm_t *as, uint op) {
130-
emit(as, op | ARM_CC_AL);
129+
emit(as, op | ASM_ARM_CC_AL);
131130
}
132131

133132
// Basic instructions without condition code
@@ -178,7 +177,7 @@ void asm_arm_bkpt(asm_arm_t *as) {
178177

179178
// locals:
180179
// - stored on the stack in ascending order
181-
// - numbered 0 through as->num_locals-1
180+
// - numbered 0 through num_locals-1
182181
// - SP points to first local
183182
//
184183
// | SP
@@ -194,30 +193,36 @@ void asm_arm_entry(asm_arm_t *as, int num_locals) {
194193
}
195194

196195
as->stack_adjust = 0;
197-
as->num_locals = num_locals;
198-
as->push_reglist = 1 << REG_R1 | 1 << REG_R2 | 1 << REG_R3 | 1 << REG_R4
199-
| 1 << REG_R5 | 1 << REG_R6 | 1 << REG_R7 | 1 << REG_R8;
196+
as->push_reglist = 1 << ASM_ARM_REG_R1
197+
| 1 << ASM_ARM_REG_R2
198+
| 1 << ASM_ARM_REG_R3
199+
| 1 << ASM_ARM_REG_R4
200+
| 1 << ASM_ARM_REG_R5
201+
| 1 << ASM_ARM_REG_R6
202+
| 1 << ASM_ARM_REG_R7
203+
| 1 << ASM_ARM_REG_R8;
200204

201205
// Only adjust the stack if there are more locals than usable registers
202206
if(num_locals > 3) {
203207
as->stack_adjust = num_locals * 4;
204208
// Align stack to 8 bytes
205-
if(as->num_locals & 1)
209+
if (num_locals & 1) {
206210
as->stack_adjust += 4;
211+
}
207212
}
208213

209-
emit_al(as, asm_arm_op_push(as->push_reglist | 1 << REG_LR));
214+
emit_al(as, asm_arm_op_push(as->push_reglist | 1 << ASM_ARM_REG_LR));
210215
if (as->stack_adjust > 0) {
211-
emit_al(as, asm_arm_op_sub_imm(REG_SP, REG_SP, as->stack_adjust));
216+
emit_al(as, asm_arm_op_sub_imm(ASM_ARM_REG_SP, ASM_ARM_REG_SP, as->stack_adjust));
212217
}
213218
}
214219

215220
void asm_arm_exit(asm_arm_t *as) {
216221
if (as->stack_adjust > 0) {
217-
emit_al(as, asm_arm_op_add_imm(REG_SP, REG_SP, as->stack_adjust));
222+
emit_al(as, asm_arm_op_add_imm(ASM_ARM_REG_SP, ASM_ARM_REG_SP, as->stack_adjust));
218223
}
219224

220-
emit_al(as, asm_arm_op_pop(as->push_reglist | (1 << REG_PC)));
225+
emit_al(as, asm_arm_op_pop(as->push_reglist | (1 << ASM_ARM_REG_PC)));
221226
}
222227

223228
void asm_arm_label_assign(asm_arm_t *as, uint label) {
@@ -289,8 +294,8 @@ void asm_arm_cmp_reg_reg(asm_arm_t *as, uint rd, uint rn) {
289294

290295
void asm_arm_less_op(asm_arm_t *as, uint rd, uint rn, uint rm) {
291296
asm_arm_cmp_reg_reg(as, rn, rm); // cmp rn, rm
292-
emit(as, asm_arm_op_mov_imm(rd, 1) | ARM_CC_LT); // movlt rd, #1
293-
emit(as, asm_arm_op_mov_imm(rd, 0) | ARM_CC_GE); // movge rd, #0
297+
emit(as, asm_arm_op_mov_imm(rd, 1) | ASM_ARM_CC_LT); // movlt rd, #1
298+
emit(as, asm_arm_op_mov_imm(rd, 0) | ASM_ARM_CC_GE); // movge rd, #0
294299
}
295300

296301
void asm_arm_add_reg(asm_arm_t *as, uint rd, uint rn, uint rm) {
@@ -300,13 +305,13 @@ void asm_arm_add_reg(asm_arm_t *as, uint rd, uint rn, uint rm) {
300305

301306
void asm_arm_mov_reg_local_addr(asm_arm_t *as, uint rd, int local_num) {
302307
// add rd, sp, #local_num*4
303-
emit_al(as, asm_arm_op_add_imm(rd, REG_SP, local_num << 2));
308+
emit_al(as, asm_arm_op_add_imm(rd, ASM_ARM_REG_SP, local_num << 2));
304309
}
305310

306311
void asm_arm_bcc_label(asm_arm_t *as, int cond, uint label) {
307312
assert(label < as->max_num_labels);
308-
int dest = as->label_offsets[label];
309-
int rel = dest - as->code_offset;
313+
mp_uint_t dest = as->label_offsets[label];
314+
mp_int_t rel = dest - as->code_offset;
310315
rel -= 8; // account for instruction prefetch, PC is 8 bytes ahead of this instruction
311316
rel >>= 2; // in ARM mode the branch target is 32-bit aligned, so the 2 LSB are omitted
312317

@@ -318,21 +323,21 @@ void asm_arm_bcc_label(asm_arm_t *as, int cond, uint label) {
318323
}
319324

320325
void asm_arm_b_label(asm_arm_t *as, uint label) {
321-
asm_arm_bcc_label(as, ARM_CC_AL, label);
326+
asm_arm_bcc_label(as, ASM_ARM_CC_AL, label);
322327
}
323328

324329
void asm_arm_bl_ind(asm_arm_t *as, void *fun_ptr, uint fun_id, uint reg_temp) {
325330
// If the table offset fits into the ldr instruction
326331
if(fun_id < (0x1000 / 4)) {
327-
emit_al(as, asm_arm_op_mov_reg(REG_LR, REG_PC)); // mov lr, pc
332+
emit_al(as, asm_arm_op_mov_reg(ASM_ARM_REG_LR, ASM_ARM_REG_PC)); // mov lr, pc
328333
emit_al(as, 0x597f000 | (fun_id << 2)); // ldr pc, [r7, #fun_id*4]
329334
return;
330335
}
331336

332337
emit_al(as, 0x59f0004 | (reg_temp << 12)); // ldr rd, [pc, #4]
333338
// Set lr after fun_ptr
334-
emit_al(as, asm_arm_op_add_imm(REG_LR, REG_PC, 4)); // add lr, pc, #4
335-
emit_al(as, asm_arm_op_mov_reg(REG_PC, reg_temp)); // mov pc, reg_temp
339+
emit_al(as, asm_arm_op_add_imm(ASM_ARM_REG_LR, ASM_ARM_REG_PC, 4)); // add lr, pc, #4
340+
emit_al(as, asm_arm_op_mov_reg(ASM_ARM_REG_PC, reg_temp)); // mov pc, reg_temp
336341
emit(as, (uint) fun_ptr);
337342
}
338343

‎py/asmarm.h‎

Lines changed: 34 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -28,41 +28,41 @@
2828
#define ASM_ARM_PASS_COMPUTE (1)
2929
#define ASM_ARM_PASS_EMIT (2)
3030

31-
#define REG_R0 (0)
32-
#define REG_R1 (1)
33-
#define REG_R2 (2)
34-
#define REG_R3 (3)
35-
#define REG_R4 (4)
36-
#define REG_R5 (5)
37-
#define REG_R6 (6)
38-
#define REG_R7 (7)
39-
#define REG_R8 (8)
40-
#define REG_R9 (9)
41-
#define REG_R10 (10)
42-
#define REG_R11 (11)
43-
#define REG_R12 (12)
44-
#define REG_R13 (13)
45-
#define REG_R14 (14)
46-
#define REG_R15 (15)
47-
#define REG_SP (REG_R13)
48-
#define REG_LR (REG_R14)
49-
#define REG_PC (REG_R15)
31+
#define ASM_ARM_REG_R0 (0)
32+
#define ASM_ARM_REG_R1 (1)
33+
#define ASM_ARM_REG_R2 (2)
34+
#define ASM_ARM_REG_R3 (3)
35+
#define ASM_ARM_REG_R4 (4)
36+
#define ASM_ARM_REG_R5 (5)
37+
#define ASM_ARM_REG_R6 (6)
38+
#define ASM_ARM_REG_R7 (7)
39+
#define ASM_ARM_REG_R8 (8)
40+
#define ASM_ARM_REG_R9 (9)
41+
#define ASM_ARM_REG_R10 (10)
42+
#define ASM_ARM_REG_R11 (11)
43+
#define ASM_ARM_REG_R12 (12)
44+
#define ASM_ARM_REG_R13 (13)
45+
#define ASM_ARM_REG_R14 (14)
46+
#define ASM_ARM_REG_R15 (15)
47+
#define ASM_ARM_REG_SP (ASM_ARM_REG_R13)
48+
#define ASM_ARM_REG_LR (ASM_ARM_REG_R14)
49+
#define ASM_ARM_REG_PC (ASM_ARM_REG_R15)
5050

51-
#define ARM_CC_EQ (0x0 << 28)
52-
#define ARM_CC_NE (0x1 << 28)
53-
#define ARM_CC_CS (0x2 << 28)
54-
#define ARM_CC_CC (0x3 << 28)
55-
#define ARM_CC_MI (0x4 << 28)
56-
#define ARM_CC_PL (0x5 << 28)
57-
#define ARM_CC_VS (0x6 << 28)
58-
#define ARM_CC_VC (0x7 << 28)
59-
#define ARM_CC_HI (0x8 << 28)
60-
#define ARM_CC_LS (0x9 << 28)
61-
#define ARM_CC_GE (0xa << 28)
62-
#define ARM_CC_LT (0xb << 28)
63-
#define ARM_CC_GT (0xc << 28)
64-
#define ARM_CC_LE (0xd << 28)
65-
#define ARM_CC_AL (0xe << 28)
51+
#define ASM_ARM_CC_EQ (0x0 << 28)
52+
#define ASM_ARM_CC_NE (0x1 << 28)
53+
#define ASM_ARM_CC_CS (0x2 << 28)
54+
#define ASM_ARM_CC_CC (0x3 << 28)
55+
#define ASM_ARM_CC_MI (0x4 << 28)
56+
#define ASM_ARM_CC_PL (0x5 << 28)
57+
#define ASM_ARM_CC_VS (0x6 << 28)
58+
#define ASM_ARM_CC_VC (0x7 << 28)
59+
#define ASM_ARM_CC_HI (0x8 << 28)
60+
#define ASM_ARM_CC_LS (0x9 << 28)
61+
#define ASM_ARM_CC_GE (0xa << 28)
62+
#define ASM_ARM_CC_LT (0xb << 28)
63+
#define ASM_ARM_CC_GT (0xc << 28)
64+
#define ASM_ARM_CC_LE (0xd << 28)
65+
#define ASM_ARM_CC_AL (0xe << 28)
6666

6767
typedef struct _asm_arm_t asm_arm_t;
6868

‎py/asmthumb.c‎

Lines changed: 16 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -68,18 +68,7 @@ void asm_thumb_free(asm_thumb_t *as, bool free_code) {
6868
if (free_code) {
6969
MP_PLAT_FREE_EXEC(as->code_base, as->code_size);
7070
}
71-
/*
72-
if (as->label != NULL) {
73-
int i;
74-
for (i = 0; i < as->label->len; ++i)
75-
{
76-
Label *lab = &g_array_index(as->label, Label, i);
77-
if (lab->unresolved != NULL)
78-
g_array_free(lab->unresolved, true);
79-
}
80-
g_array_free(as->label, true);
81-
}
82-
*/
71+
m_del(mp_uint_t, as->label_offsets, as->max_num_labels);
8372
m_del_obj(asm_thumb_t, as);
8473
}
8574

@@ -284,23 +273,23 @@ void asm_thumb_op32(asm_thumb_t *as, uint op1, uint op2) {
284273
#define OP_FORMAT_2(op, rlo_dest, rlo_src, src_b) ((op) | ((src_b) << 6) | ((rlo_src) << 3) | (rlo_dest))
285274

286275
void asm_thumb_format_2(asm_thumb_t *as, uint op, uint rlo_dest, uint rlo_src, int src_b) {
287-
assert(rlo_dest < REG_R8);
288-
assert(rlo_src < REG_R8);
276+
assert(rlo_dest < ASM_THUMB_REG_R8);
277+
assert(rlo_src < ASM_THUMB_REG_R8);
289278
asm_thumb_op16(as, OP_FORMAT_2(op, rlo_dest, rlo_src, src_b));
290279
}
291280

292281
#define OP_FORMAT_3(op, rlo, i8) ((op) | ((rlo) << 8) | (i8))
293282

294283
void asm_thumb_format_3(asm_thumb_t *as, uint op, uint rlo, int i8) {
295-
assert(rlo < REG_R8);
284+
assert(rlo < ASM_THUMB_REG_R8);
296285
asm_thumb_op16(as, OP_FORMAT_3(op, rlo, i8));
297286
}
298287

299288
#define OP_FORMAT_4(op, rlo_dest, rlo_src) ((op) | ((rlo_src) << 3) | (rlo_dest))
300289

301290
void asm_thumb_format_4(asm_thumb_t *as, uint op, uint rlo_dest, uint rlo_src) {
302-
assert(rlo_dest < REG_R8);
303-
assert(rlo_src < REG_R8);
291+
assert(rlo_dest < ASM_THUMB_REG_R8);
292+
assert(rlo_src < ASM_THUMB_REG_R8);
304293
asm_thumb_op16(as, OP_FORMAT_4(op, rlo_dest, rlo_src));
305294
}
306295

@@ -331,7 +320,7 @@ void asm_thumb_mov_reg_reg(asm_thumb_t *as, uint reg_dest, uint reg_src) {
331320

332321
// if loading lo half with movw, the i16 value will be zero extended into the r32 register!
333322
STATIC void asm_thumb_mov_reg_i16(asm_thumb_t *as, uint mov_op, uint reg_dest, int i16_src) {
334-
assert(reg_dest < REG_R15);
323+
assert(reg_dest < ASM_THUMB_REG_R15);
335324
// mov[wt] reg_dest, #i16_src
336325
asm_thumb_op32(as, mov_op | ((i16_src >> 1) & 0x0400) | ((i16_src >> 12) & 0xf), ((i16_src << 4) & 0x7000) | (reg_dest << 8) | (i16_src & 0xff));
337326
}
@@ -409,14 +398,14 @@ void asm_thumb_mov_reg_i32_aligned(asm_thumb_t *as, uint reg_dest, int i32) {
409398
#define OP_LDR_FROM_SP_OFFSET(rlo_dest, word_offset) (0x9800 | ((rlo_dest) << 8) | ((word_offset) & 0x00ff))
410399

411400
void asm_thumb_mov_local_reg(asm_thumb_t *as, int local_num, uint rlo_src) {
412-
assert(rlo_src < REG_R8);
401+
assert(rlo_src < ASM_THUMB_REG_R8);
413402
int word_offset = local_num;
414403
assert(as->pass < ASM_THUMB_PASS_EMIT || word_offset >= 0);
415404
asm_thumb_op16(as, OP_STR_TO_SP_OFFSET(rlo_src, word_offset));
416405
}
417406

418407
void asm_thumb_mov_reg_local(asm_thumb_t *as, uint rlo_dest, int local_num) {
419-
assert(rlo_dest < REG_R8);
408+
assert(rlo_dest < ASM_THUMB_REG_R8);
420409
int word_offset = local_num;
421410
assert(as->pass < ASM_THUMB_PASS_EMIT || word_offset >= 0);
422411
asm_thumb_op16(as, OP_LDR_FROM_SP_OFFSET(rlo_dest, word_offset));
@@ -425,7 +414,7 @@ void asm_thumb_mov_reg_local(asm_thumb_t *as, uint rlo_dest, int local_num) {
425414
#define OP_ADD_REG_SP_OFFSET(rlo_dest, word_offset) (0xa800 | ((rlo_dest) << 8) | ((word_offset) & 0x00ff))
426415

427416
void asm_thumb_mov_reg_local_addr(asm_thumb_t *as, uint rlo_dest, int local_num) {
428-
assert(rlo_dest < REG_R8);
417+
assert(rlo_dest < ASM_THUMB_REG_R8);
429418
int word_offset = local_num;
430419
assert(as->pass < ASM_THUMB_PASS_EMIT || word_offset >= 0);
431420
asm_thumb_op16(as, OP_ADD_REG_SP_OFFSET(rlo_dest, word_offset));
@@ -439,7 +428,7 @@ void asm_thumb_b_label(asm_thumb_t *as, uint label) {
439428
mp_uint_t dest = get_label_dest(as, label);
440429
mp_int_t rel = dest - as->code_offset;
441430
rel -= 4; // account for instruction prefetch, PC is 4 bytes ahead of this instruction
442-
if (dest >= 0 && rel <= -4) {
431+
if (dest != -1 && rel <= -4) {
443432
// is a backwards jump, so we know the size of the jump on the first pass
444433
// calculate rel assuming 12 bit relative jump
445434
if (SIGNED_FIT12(rel)) {
@@ -462,7 +451,7 @@ void asm_thumb_bcc_label(asm_thumb_t *as, int cond, uint label) {
462451
mp_uint_t dest = get_label_dest(as, label);
463452
mp_int_t rel = dest - as->code_offset;
464453
rel -= 4; // account for instruction prefetch, PC is 4 bytes ahead of this instruction
465-
if (dest >= 0 && rel <= -4) {
454+
if (dest != -1 && rel <= -4) {
466455
// is a backwards jump, so we know the size of the jump on the first pass
467456
// calculate rel assuming 9 bit relative jump
468457
if (SIGNED_FIT9(rel)) {
@@ -482,17 +471,17 @@ void asm_thumb_bcc_label(asm_thumb_t *as, int cond, uint label) {
482471

483472
void asm_thumb_bl_ind(asm_thumb_t *as, void *fun_ptr, uint fun_id, uint reg_temp) {
484473
/* TODO make this use less bytes
485-
uint rlo_base = REG_R3;
486-
uint rlo_dest = REG_R7;
474+
uint rlo_base = ASM_THUMB_REG_R3;
475+
uint rlo_dest = ASM_THUMB_REG_R7;
487476
uint word_offset = 4;
488477
asm_thumb_op16(as, 0x0000);
489478
asm_thumb_op16(as, 0x6800 | (word_offset << 6) | (rlo_base << 3) | rlo_dest); // ldr rlo_dest, [rlo_base, #offset]
490-
asm_thumb_op16(as, 0x4780 | (REG_R9 << 3)); // blx reg
479+
asm_thumb_op16(as, 0x4780 | (ASM_THUMB_REG_R9 << 3)); // blx reg
491480
*/
492481

493482
if (fun_id < 32) {
494483
// load ptr to function from table, indexed by fun_id (must be in range 0-31); 4 bytes
495-
asm_thumb_op16(as, OP_FORMAT_9_10(ASM_THUMB_FORMAT_9_LDR | ASM_THUMB_FORMAT_9_WORD_TRANSFER, reg_temp, REG_R7, fun_id));
484+
asm_thumb_op16(as, OP_FORMAT_9_10(ASM_THUMB_FORMAT_9_LDR | ASM_THUMB_FORMAT_9_WORD_TRANSFER, reg_temp, ASM_THUMB_REG_R7, fun_id));
496485
asm_thumb_op16(as, OP_BLX(reg_temp));
497486
} else {
498487
// load ptr to function into register using immediate; 6 bytes

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