Enable VFIO CXL core support on amd64 and arm64 to allow CXL Type-2
device passthrough via vfio-pci.
Signed-off-by: Jiandi An <email address hidden>
(backported from commit 74b6b99bcd80 from https://github.com/JiandiAnNVIDIA/NV-Kernels.git cxl-vfio_2026-04-23)
[kobak: Applied the equivalent annotation to debian.master/config/annotations because the 7.0 HWE target does not carry debian.nvidia-6.17/config/annotations.]
Signed-off-by: Koba Ko <email address hidden>
Acked-by: Jamie Nguyen <email address hidden>
Acked-by: Matthew R. Ochs <email address hidden>
Acked-by: Carol L Soto <email address hidden>
Signed-off-by: Brad Figg <email address hidden>
Add vfio_cxl_reset() to drive a CXL protocol reset on behalf of a guest.
Unlike cxl_do_reset(), this path skips host memory offlining since the
DPA region is guest memory. The function takes memory_lock for the full
sequence, calls vfio_cxl_prepare_reset() to zap DPA region PTEs, drives
the hardware via cxl_dev_reset_locked(), which performs
pci_dev_save_and_disable(), cxl_dev_reset(), sibling CXL.cachemem
coordination, and pci_dev_restore() under the CXL reset mutex, then calls
vfio_cxl_finish_reset() to reinitialise emulated state.
STATUS2 outcome bits (CXL_RESET_COMPLETE / CXL_RESET_ERROR) are written
back to vconfig after the reset so the guest can poll for the result
without reading hardware. cxl_save_dvsec() / cxl_restore_dvsec() cover
CTRL, CTRL2, range_base_*, and LOCK; STATUS2 is not saved or restored
across the reset, so the hardware value is re-read after restore (it
will have both outcome bits clear) and the outcome is stamped on top.
When the guest writes INIT_CXL_RST into DVSEC CONTROL2, invoke
vfio_cxl_reset() to perform a CXL protocol reset. The bit is not
forwarded to hardware; cxl_dev_reset() drives the reset sequence
directly. Silently drop writes on devices that do not advertise
RST_CAPABLE to avoid log noise for the reserved-bit case.
Signed-off-by: Manish Honap <email address hidden>
Signed-off-by: Jiandi An <email address hidden>
(cherry-picked from commit 67c66e735df5762cfeb7b80e4fdf0815451899f9 from https://github.com/JiandiAnNVIDIA/NV-Kernels.git cxl-vfio_2026-04-23)
Signed-off-by: Koba Ko <email address hidden>
Acked-by: Jamie Nguyen <email address hidden>
Acked-by: Matthew R. Ochs <email address hidden>
Acked-by: Carol L Soto <email address hidden>
Signed-off-by: Brad Figg <email address hidden>
STATUS2 was read directly from hardware while all other DVSEC registers
were served from the vconfig shadow. This created two problems:
1. VOLATILE_HDM_PRES_ERROR (RW1CS, bit 3): guest writes cleared the
hardware bit but the shadow was not updated, so subsequent reads still
returned the set bit from hardware (which the hardware had cleared).
2. CXL_RESET_COMPLETE and CXL_RESET_ERROR (bits 1-2): these outcome bits
will be written by vfio_cxl_reset() into the shadow after a protocol
reset. Hardware does not update them on its own; serving reads from
hardware would hide the outcome from the guest.
Add STATUS2 to the read switch so reads come from the shadow, and update
cxl_dvsec_status2_write() to mirror VOLATILE_HDM_PRES_ERROR clears into
the shadow after forwarding to hardware.
Signed-off-by: Manish Honap <email address hidden>
Signed-off-by: Jiandi An <email address hidden>
(backported from commit 14fbdcb4d592891c269d052317cc10b640aa4096 from https://github.com/JiandiAnNVIDIA/NV-Kernels.git cxl-vfio_2026-04-23)
Signed-off-by: Koba Ko <email address hidden>
Acked-by: Jamie Nguyen <email address hidden>
Acked-by: Matthew R. Ochs <email address hidden>
Acked-by: Carol L Soto <email address hidden>
Signed-off-by: Brad Figg <email address hidden>
After FLR, reinit_comp_regs() re-reads HDM decoder registers from
hardware into comp_reg_virt[]. Hardware is not all-zeros at this
point: pci_dev_restore() ran first and re-committed the pre-reset
host-physical decoder bases into the registers. reinit_comp_regs()
therefore overwrites the emulated guest-physical bases that the device
manager programmed with the host-physical bases used by the host CXL
core. The kernel provides no notification that BASE was overwritten,
so the emulated GPA bases are silently lost.
The same issue affects the CTRL LOCK bit: FLR clears it in hardware
and pci_dev_restore() does not re-apply it, so a decoder that the
guest had locked re-emerges from reset with LOCK clear in shadow.
Add vfio_cxl_reinit_hdm_shadow() which snapshots BASE_LOW, BASE_HIGH,
and the CTRL LOCK bit from the shadow before calling
reinit_comp_regs(), then writes them back after, keeping the emulated
decoder consistent with what the guest programmed.
Signed-off-by: Manish Honap <email address hidden>
Signed-off-by: Jiandi An <email address hidden>
(cherry-picked from commit 9e0e291bfc29f40e5db40256353b89d34fd93ddf from https://github.com/JiandiAnNVIDIA/NV-Kernels.git cxl-vfio_2026-04-23)
Signed-off-by: Koba Ko <email address hidden>
Acked-by: Jamie Nguyen <email address hidden>
Acked-by: Matthew R. Ochs <email address hidden>
Acked-by: Carol L Soto <email address hidden>
Signed-off-by: Brad Figg <email address hidden>
A reset caller may disable Memory Space to quiesce device DMA before
issuing the reset. The reset path saves and restores PCI_COMMAND via
pci_dev_save_and_disable() and pci_dev_restore(). If Memory Space was
disabled before FLR, it will be restored in the disabled state.
vfio_cxl_finish_reset() reads HDM decoder registers through the
component register BAR immediately after reset. Accessing a BAR with
Memory Space disabled produces an Unsupported Request completion; on
platforms that promote UR to a fatal error this triggers DPC.
Add vfio_cxl_enable_memory_space() and call it at the start of
vfio_cxl_finish_reset() before touching any BAR.
Signed-off-by: Manish Honap <email address hidden>
Signed-off-by: Jiandi An <email address hidden>
(backported from commit 5071d3b07627ab1fc42f0149352a2704907f8364 from https://github.com/JiandiAnNVIDIA/NV-Kernels.git cxl-vfio_2026-04-23)
Signed-off-by: Koba Ko <email address hidden>
Acked-by: Jamie Nguyen <email address hidden>
Acked-by: Matthew R. Ochs <email address hidden>
Acked-by: Carol L Soto <email address hidden>
Signed-off-by: Brad Figg <email address hidden>
