Low Voltage, Low Power VLSI SubsystemsDetails design techniques for the low power circuitry required by the various miniaturized business and consumer products driving the electronics market. This book teaches techniques in low power CMOS/BICMOS VLSI subsystems design, covering the challenges facing integrated circuit and system designers in creating low-power VLSI subsystems. |
Contents
LowPower CMOS VLSI Design | 1 |
Circuit Techniques for LowPower Design | 41 |
LowVoltage LowPower Adders | 63 |
Copyright | |
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2's complement 6T cell algorithm architecture bias binary bit-lines Booth encoder Braun multiplier buffer cache capacitance carry propagation channel length charge pump chip clock CMOS Computer conventional Cout cycle delay depletion region device Digital doping drain DRAM dynamic EEPROM effect electron Figure flash memory floating gate full adder function gate oxide high-speed IEEE implementation increase input latch leakage current logic Low Power low-power low-voltage memory cell MOSFET nMOS node operands operation output oxide thickness partial product percent performance PMOS power consumption power dissipation power supply voltage precharge processor reduce schematic SDRAM sense amplifier short channel shown in Fig signal Solid-State Circuits speed SRAM SRAM cell static stored substrate subthreshold leakage switching techniques threshold voltage transistor tunneling VLSI voltage scaling Wallace tree width word-line XOR gate